公开(公告)号：JP2000216354A

公开(公告)日：2000-08-04

申请号：JP2000005490

申请日：2000-01-14

Applicant: IBM ,  SIEMENS AG

Inventor： MANDELMAN JACK ,  RADENS CARL ,  GRUENING ULRIKE

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an embedded self-aligned strap in a deep storage trench. SOLUTION: A spacer 42/52 is formed on the wall face of a recess on an already filled deep trench capacitor 30. A plug 46/54 is formed within the region between spacers. A photoresist is stuck onto the spacer 42/54 and the plug 46/54 and a peripheral material 40, and a part of the plug 46/54, the spacer 42/52, and the material 40 is exposed. The spacer part not covered with the photoresist is selectively etched. A board and a trench part exposed by the removal of the spacer are selectively etched. An isolation region 58 is formed within the space made etching.

公开(公告)号：JP2000196045A

公开(公告)日：2000-07-14

申请号：JP37569999

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL ,  GRUENING ULRIKE ,  DEBROSSE JOHN ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain necessary insulation between a capacitor for storage and a transistor in a memory cell, using both a capacitor for storage in a vertical trench and a vertical transistor. SOLUTION: One memory cell formed in a semiconductor main body 10 includes a polycrystalline silicon packing part 22 as a capacitor for storage and one field-effect transistor. This field-effect transistor includes a source 43 formed in the sidewall of a trench, a drain 42 formed in the semiconductor main body and provided with a surface in common with the upper face of the semiconductor main body, a channel region including both vertical and horizontal parts, and a polycrystalline silicon gate at the upper part of the trench. Thus, an insulating oxide layer 28 at the top end of the polycrystalline silicon packing part, which is useful as a storage node and the polycrystalline silicon packing part which is useful as a gate conductor can be obtained in this process for manufacturing.

公开(公告)号：JP2000022101A

公开(公告)日：2000-01-21

申请号：JP15133899

申请日：1999-05-31

Applicant: IBM ,  SIEMENS AG

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce remarkably the distributed series resistance of trench electrodes, by manufacturing trench capacitors using a method of forming heat- resistant metallic salicide materials on the trench regions having low trench capacitors. SOLUTION: A narrow upper region 16a and a wide lower region 16b are filled with ploysilicon layers 26 and the polysilicon layers 26 are planarized. Next, the polysilicon layers 26 are recessed, then conformal heat-resistant metallic layers 30 are adhered. After that, the salicide is formed at the interface between the heat-resistant metal in the region 16b and the polysilicon by annealing. As a result, a heat-resistant metallic salicide layer 32 is formed in the wide lower trench region 16b. It is preferable that the heat-resistant metallic salicide layer is not formed in the narrow upper trench region 16b. Next, the heat-resistant metallic layer 30 remained in the upper layer 16a is removed. Then, the additional polysilicon is filled in the trench. After that, the capacitor structure is planarized.

公开(公告)号：JPH11176930A

公开(公告)日：1999-07-02

申请号：JP26992298

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a layer which is uniform in flatness and thickness on a semiconductor chip or on a semiconductor device provided with a trench. SOLUTION: An oxide thermal pad layer 104 is formed on a semiconductor substrate 102 through a thermal oxidation method, a nitride insulating layer 106, a buffer layer 108 of oxide or preferably TEOS(tetraethyl oxosilane), and a SiN mask layer 110 are formed thereon through a CVD(chemical vapor deposition) method, and a hard mask layer 112 containing BSG(borosilicate glass) or TEOS is formed on the mask layer 110. Then, a semiconductor device is manufactured, a trench is provided to the device, filler is filled, a polishing is carried out up to a pad stop, and an etching operation is carried out using the buffer layer as an etching stopper for removing the pad stop and the buffer layer, whereby a surface layer which is nearly flat and uniform in thickness can be obtained.

公开(公告)号：DE60129605D1

公开(公告)日：2007-09-06

申请号：DE60129605

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：AT519228T

公开(公告)日：2011-08-15

申请号：AT00103964

申请日：2000-02-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

公开(公告)号：HK1042377A1

公开(公告)日：2002-08-09

申请号：HK02102046

申请日：2002-03-18

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J

IPC: H01L20060101 ,  H01L

公开(公告)号：DE60129605T2

公开(公告)日：2008-06-05

申请号：DE60129605

申请日：2001-11-28

Applicant: IBM ,  QIMONDA NORTH AMERICA CORP

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：DE69809868T2

公开(公告)日：2003-10-09

申请号：DE69809868

申请日：1998-09-25

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/762

Abstract: A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

公开(公告)号：DE69809868D1

公开(公告)日：2003-01-16

申请号：DE69809868

申请日：1998-09-25

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/762

Abstract: A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.