公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：WO0245130A3

公开(公告)日：2004-01-08

申请号：PCT/US0144625

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L27/10 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

公开(公告)号：WO0201567A3

公开(公告)日：2002-02-25

申请号：PCT/US0120221

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：WO0117010A9

公开(公告)日：2002-09-19

申请号：PCT/US0023850

申请日：2000-08-30

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： AKATSU HIROYUKI ,  DIVAKARUNI RAMACHANDRA ,  LEE GILL YOUNG

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10894

Abstract: There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer (36) and an outer spacer (38), the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.

Abstract translation: 公开了形成用于半导体器件的栅极导体的工艺。 该方法开始于提供其上形成有栅极堆叠的半导体衬底的步骤，栅叠层包括侧壁。 电介质间隔物形成在栅极导体侧壁上，电介质隔离物包括内部间隔物（36）和外部间隔物（38），外部间隔物是掺杂的玻璃材料。 离子在介质间隔物的外侧注入到半导体衬底中。 然后拆下外隔离物。

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：DE60129605D1

公开(公告)日：2007-09-06

申请号：DE60129605

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：DE10226569A1

公开(公告)日：2003-01-16

申请号：DE10226569

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  DEV PRAKASH ,  MALIK RAJEEV ,  NESBIT LARRY

IPC: H01L21/8242 ,  H01L27/108

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

公开(公告)号：DE60133214D1

公开(公告)日：2008-04-24

申请号：DE60133214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：US6444548B2

公开(公告)日：2002-09-03

申请号：US25781799

申请日：1999-02-25

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  LI YUJUN ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/22 ,  H01L21/38 ,  H01L21/425 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10861 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract translation: 一种用于制造集成电路器件的集成电路器件和方法，包括形成与存储器件相邻的图案化栅叠层，以包括与存储器件相邻的存储节点扩散区域和与存储节点扩散区域相对的位线接触扩散区域， 在存储节点扩散区域和位线接触扩散区域中形成杂质，在图案化的栅极堆叠上形成绝缘体层，从位线接触扩散区域去除绝缘体层的一部分，以沿着图案化的栅极叠层的一部分相邻形成侧壁间隔物 所述位线接触扩散区域将卤素注入物注入到所述位线接触扩散区域中，其中所述绝缘体层不从所述第二扩散区域阻挡所述卤素注入并退火所述集成电路器件以在所述杂质之前驱动所述卤素注入。