3.
    发明专利
    未知

    公开(公告)号:DE10307822A1

    公开(公告)日:2003-11-06

    申请号:DE10307822

    申请日:2003-02-24

    Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

    4.
    发明专利
    未知

    公开(公告)号:AT519228T

    公开(公告)日:2011-08-15

    申请号:AT00103964

    申请日:2000-02-25

    Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

    5.
    发明专利
    未知

    公开(公告)号:DE10307822B4

    公开(公告)日:2005-08-18

    申请号:DE10307822

    申请日:2003-02-24

    Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
    7.
    发明申请
    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
    双端口增益电池与侧面和顶部门控读取晶体管

    公开(公告)号:WO2007023011A2

    公开(公告)日:2007-03-01

    申请号:PCT/EP2006063581

    申请日:2006-06-27

    CPC classification number: H01L27/108 H01L27/10829 H01L27/10867 H01L27/1203

    Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    Abstract translation: 用绝缘体上硅(SOI)CMOS技术制造用于制造致密(20或18平方)布局的DRAM存储器单元和工艺序列。 具体而言,本发明提供了与现有SOI CMOS技术兼容的密集,高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言,存储器单元包括分别设置有栅极,源极和漏极的第一晶体管; 第二晶体管,分别具有第一栅极,第二栅极,源极和漏极; 以及具有第一端子的电容器,其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

    METHOD FOR WRAPPED-GATE MOSFET
    9.
    发明公开
    METHOD FOR WRAPPED-GATE MOSFET 审中-公开
    方法包裹的栅极MOSFET

    公开(公告)号:EP1436843A4

    公开(公告)日:2008-11-26

    申请号:EP02780350

    申请日:2002-09-17

    Applicant: IBM

    Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

    SEMICONDUCTOR INTEGRATED CIRCUIT
    10.
    发明专利

    公开(公告)号:JP2000031425A

    公开(公告)日:2000-01-28

    申请号:JP17893899

    申请日:1999-06-24

    Applicant: SIEMENS AG IBM

    Abstract: PROBLEM TO BE SOLVED: To reduce the rough surface on a side wall of a trench of a trench capacitor by forming the trench capacitor in the shape of a bottle with the lower part of the treanch being larger than the upper part and covering a collar and an epitaxial buried plate from inside with a node dielectric. SOLUTION: A trench capacitor 310 included in a DRAM cell 300 is formed in a silicon wafer substrate 301. A lower part of a trench has a larger diameter or width WL than the diameter or width WU of an upper part. The trench of such a shape is called a bottle trench. And, an epitaxial silicon (epi) layer 365 covers the lower part of the trench below a collar 368 from inside. The epi is doped with an n-type dopant such as As or P and is used as a buried plate of a capacitor. By covering the lower part of the trench by the epi layer from inside, the rough surface to be formed with a node dielectric can be reduced.

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