公开(公告)号：WO03005447A8

公开(公告)日：2004-02-19

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：WO03005447A2

公开(公告)日：2003-01-16

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。 该工艺消除了对M0金属化层的需求。

公开(公告)号：DE10307822A1

公开(公告)日：2003-11-06

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：AT519228T

公开(公告)日：2011-08-15

申请号：AT00103964

申请日：2000-02-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

公开(公告)号：DE10307822B4

公开(公告)日：2005-08-18

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：EP1869709A4

公开(公告)日：2008-07-16

申请号：EP06749815

申请日：2006-04-12

Applicant: IBM

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

公开(公告)号：WO2007023011A2

公开(公告)日：2007-03-01

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。 具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：EP1599904A4

公开(公告)日：2006-04-26

申请号：EP02786852

申请日：2002-12-03

Applicant: IBM

Inventor： MANDELMAN JACK ,  VOLDMAN STEVEN H

IPC: H01L21/336 ,  H01L23/62 ,  H01L27/02 ,  H01L27/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/7841 ,  H01L27/0255 ,  H01L27/1203 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78684 ,  H01L2029/7857

Abstract: An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (50) (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate (60). The gate (60) may be connected to the external electrode (51) being protected to make a self-activating device and may be connected to a reference voltage (92). The device may be used in digital or analog circuits.

公开(公告)号：EP1436843A4

公开(公告)日：2008-11-26

申请号：EP02780350

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L29/76 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

公开(公告)号：JP2000031425A

公开(公告)日：2000-01-28

申请号：JP17893899

申请日：1999-06-24

Applicant: SIEMENS AG ,  IBM

Inventor： SCHREMS MARTIN ,  MANDELMAN JACK ,  HOEPFNER JOACHIM ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To reduce the rough surface on a side wall of a trench of a trench capacitor by forming the trench capacitor in the shape of a bottle with the lower part of the treanch being larger than the upper part and covering a collar and an epitaxial buried plate from inside with a node dielectric. SOLUTION: A trench capacitor 310 included in a DRAM cell 300 is formed in a silicon wafer substrate 301. A lower part of a trench has a larger diameter or width WL than the diameter or width WU of an upper part. The trench of such a shape is called a bottle trench. And, an epitaxial silicon (epi) layer 365 covers the lower part of the trench below a collar 368 from inside. The epi is doped with an n-type dopant such as As or P and is used as a buried plate of a capacitor. By covering the lower part of the trench by the epi layer from inside, the rough surface to be formed with a node dielectric can be reduced.