公开(公告)号：SG152247A1

公开(公告)日：2009-05-29

申请号：SG2009025891

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: There is provided a method of manufacturing a field effect transistor (FET) (100) that includes the steps of forming a gate structure (175) on a semiconductor substrate (105), and forming a recess (160) in the substrate and embedding a second semiconductor material (165) in the recess. The gate structure includes a gate dielectric layer (115), conductive layers (120, 130) and an insulating layer (125). Forming said gate structure includes a step of recessing the conductive layer (130) in the gate structure, and the steps of recessing the conductive layer and forming the recess (160) in the substrate are performed in a single step. There is also provided a FET device.

公开(公告)号：SG138528A1

公开(公告)日：2008-01-28

申请号：SG2007036023

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  LUN ZHAO ,  HOLT JUDSON ROBERT ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces (14A, 16A) with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate (10). Each surface recess preferably has a bottom surface (14, 16) that is parallel to the substrate surface (10A), which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces (14A, 16A) that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces (14A, 16A) of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces (14A, 16A) can be readily formed by crystallographic etching of the semiconductor substrate (10), followed by epitaxial growth of a semiconductor material.

公开(公告)号：AT521089T

公开(公告)日：2011-09-15

申请号：AT07797521

申请日：2007-05-17

Applicant: IBM

Inventor： LI JINGHONG ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

公开(公告)号：SG132642A1

公开(公告)日：2007-06-28

申请号：SG2006081384

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  TEH YOUNG WAY ,  AJMERA ATUL C

Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer (16) on each side of a gate region (14) of a substrate (12) and embedding the L-shaped spacers (16) in an oxide layer (28) so that the oxide layer (28) extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer (16). In one embodiment, the method further includes the step of removing oxide layers to expose the L-shape spacers.

公开(公告)号：SG132641A1

公开(公告)日：2007-06-28

申请号：SG2006081376

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: There is provided a method of manufacturing a field effect transistor (FET) (100) that includes the steps of forming a gate structure (175) on a semiconductor substrate (105), and forming a recess (160) in the substrate and embedding a second semiconductor material (165) in the recess. The gate structure includes a gate dielectric layer (115), conductive layers (120, 130) and an insulating layer (125). Forming said gate structure includes a step of recessing the conductive layer (130) in the gate structure, and the steps of recessing the conductive layer and forming the recess (160) in the substrate are performed in a single step. There is also provided a FET device.

公开(公告)号：SG175644A1

公开(公告)日：2011-11-28

申请号：SG2011075819

申请日：2007-02-06

Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM

Inventor： CHONG YUNG FU ,  LUO ZHIJIONG ,  JUDSON ROBERT HOLT

Abstract: METHOD TO CONTROL SOURCE/DRAIN STRESSOR PROFILES FOR STRESS ENGINEERINGAbstractAn example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.Fig.5

公开(公告)号：SG137761A1

公开(公告)日：2007-12-28

申请号：SG2007033061

申请日：2007-05-10

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHONG YUNG FU ,  LUO ZHIJIONG ,  HOLT JUDSON

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure (200) comprises a source stressor region (225) comprising a source extension stressor region (225A); and a drain stressor region (226) comprising a drain extension stressor region (226A); wherein a strained channel region (229) is formed between the source extension stessor region (225A) and the drain extension stressor region (226A), a width of said channel region (229) being defined by adjacent ends (225B, 226B) of said extension stressor regions (225A, 226A).

公开(公告)号：SG137760A1

公开(公告)日：2007-12-28

申请号：SG2007033046

申请日：2007-05-10

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHONG YUNG FU ,  DEZFULIAN KEVIN K ,  LUO ZHIJIONG ,  ZHU HUILONG

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure (200) on a substrate (202), comprising the steps of: forming a source stressor recess (225) comprising a deep source recess (219) and a source extension recess (221); forming a drain stressor recess (226) comprising a deep drain recess (220) and a drain extension recess (222); and subsequently forming a source stressor (227) in said source stressor recess (225) and a drain stressor (228) in said drain stressor recess (226). The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.