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    Ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation
    2.
    发明专利
    Ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation 有权
    在离子间隙形成的氧化物之前将氮离子注入半导体衬底

    公开(公告)号：JP2007142430A

    公开(公告)日：2007-06-07

    申请号：JP2006310944

    申请日：2006-11-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LUO ZHIJIONG ,  LI JINGHONG ,  THOMAS W DYER

    IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/26506 ,  H01L21/28247

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an FET device in which an offset spacer is formed and a sidewall spacer is formed prior to a source/drain extension forming step.
    SOLUTION: A gate electrode stack including a gate dielectric layer and a gate electrode thereon is formed. Diatomic nitrogen or nitrogen atoms, or both are implanted into a substrate except for a stack with a maximum energy of 10 keV or less for the diatomic nitrogen and a maximum energy of 5 keV or less for the nitrogen atoms at a temperature equal to or lower than 1,000°C for 30 minutes or less. Next, an offset spacer of oxide silicon is formed on a sidewall of the stack and a source/drain extension region is formed. A sidewall spacer of nitride is formed on the outer surface of the offset spacer. Next, a source/drain region is formed on the substrate except for the sidewall spacer.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于制造其中形成偏移间隔物并在源极/漏极延伸形成步骤之前形成侧壁间隔物的FET器件的方法。 解决方案：形成包括栅极电介质层和栅电极的栅电极堆叠。 将双原子氮或氮原子或二者注入基底中，除了对于双原子氮具有10keV或更小的最大能量的叠层以及在等于或等于或等于等于或等于3的温度下氮原子的最大能量为5keV或更小 1000℃以上30分钟以下。 接下来，在堆叠的侧壁上形成氧化硅的偏移间隔物，形成源极/漏极延伸区域。 在偏置间隔物的外表面上形成氮化物的侧壁间隔物。 接下来，除了侧壁间隔物之外，在基板上形成源极/漏极区域。 版权所有（C）2007，JPO＆INPIT

    MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS
    3.
    发明申请
    MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
    用于高级CMOS的单层掺杂嵌入式压电器

    公开(公告)号：WO2011133339A3

    公开(公告)日：2012-03-08

    申请号：PCT/US2011031693

    申请日：2011-04-08

    Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

    Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

    DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE
    4.
    发明申请
    DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
    DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观

    公开(公告)号：WO2011162977A3

    公开(公告)日：2012-03-15

    申请号：PCT/US2011039892

    申请日：2011-06-10

    Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

    Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

    Delta monolayer dopants epitaxy for embedded source/drain silicide
    6.
    发明专利
    Delta monolayer dopants epitaxy for embedded source/drain silicide 未知

    公开(公告)号：GB2494608B

    公开(公告)日：2013-09-04

    申请号：GB201300789

    申请日：2011-06-10

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

    Monolayer dopant embedded stressor for advanced cmos
    7.
    发明专利
    Monolayer dopant embedded stressor for advanced cmos 未知

    公开(公告)号：GB2492524A

    公开(公告)日：2013-01-02

    申请号：GB201220031

    申请日：2011-04-08

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L21/8238

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

    Stressor mit eingebetteter Dotierstoff-Monoschicht für hochentwickelten CMOS-Halbleiter
    9.
    发明专利
    Stressor mit eingebetteter Dotierstoff-Monoschicht für hochentwickelten CMOS-Halbleiter 未知

    公开(公告)号：DE112011101433T5

    公开(公告)日：2013-03-28

    申请号：DE112011101433

    申请日：2011-04-08

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

    Abstract: Es werden Halbleiterstrukturen mit eingebetteten Stressorelementen offenbart. Die offenbarten Strukturen umfassen einen FET-Gate-Stapel 18, der sich auf einer oberen Oberfläche eines Halbleitersubstrats 12 befindet. Der FET-Gate-Stapel umfasst den Source- und den Drain-Erweiterungsbereich 28, die sich in dem Halbleitersubstrat an einer Auflagefläche des FET-Gate-Stapels befinden. Zwischen dem Source- und dem Drain-Erweiterungsbereich und unterhalb des Gate-Stapels ist außerdem ein Bauelementkanal 40 vorhanden. Die Struktur umfasst weiter eingebettete Stressorelemente 34, die sich auf entgegengesetzten Seiten des FET-Gate-Stapels und in dem Halbleitersubstrat befinden. Jedes der eingebetteten Stressorelemente enthält eine untere Schicht eines ersten dotierten Epitaxie-Halbleitermaterials 36 mit einer Gitterkonstante, die sich von einer Gitterkonstante des Halbleitersubstrats unterscheidet und eine Verspannung in den Bauelementkanal überträgt, und eine obere Schicht eines zweiten dotierten Epitaxie-Halbleitermaterials 38, die sich auf der unteren Schicht befindet. Die untere Schicht des ersten dotierten Epitaxie-Halbleitermaterials weist im Vergleich mit der oberen Schicht des zweiten dotierten Epitaxie-Halbleitermaterials einen geringeren Dotierstoffgehalt auf. Die Struktur umfasst weiter eine Dotierstoff-Monoschicht, die sich in der oberen Schicht jedes der eingebetteten Stressorelemente befindet. Die Dotierstoff-Monoschicht steht mit einem Rand entweder des Source-Erweiterungsbereichs oder des Drain-Erweiterungsbereichs in direktem Kontakt.

    Delta monolayer dopants epitaxy for embedded source/drain silicide
    10.
    发明专利
    Delta monolayer dopants epitaxy for embedded source/drain silicide 未知

    公开(公告)号：GB2494608A

    公开(公告)日：2013-03-13

    申请号：GB201300789

    申请日：2011-06-10

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

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