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公开(公告)号：AT39581T
公开(公告)日：1989-01-15
申请号：AT85100105
申请日：1985-01-11
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
IPC: G06F13/28
Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.
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公开(公告)号：BR8801278A
公开(公告)日：1988-10-25
申请号：BR8801278
申请日：1988-03-22
Applicant: IBM
Inventor： LO YUAN-CHANG , MOELLER DENNIS LEE , SZAREK JOHN JOSEPH
Abstract: A microcomputer system has first, low order address, memory means (17) soldered to the planar printed circuit board and can accept further memory means (18) pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.
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公开(公告)号：FR2613094A1
公开(公告)日：1988-09-30
申请号：FR8718197
申请日：1987-12-21
Applicant: IBM
Inventor： LO YUAN-CHANG , SZAREK JOHN JOSEPH , MOELLER DENNIS LEE
Abstract: A microcomputer system has first, low order address, memory means (17) soldered to the planar printed circuit board and can accept further memory means (18) pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.
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公开(公告)号：GB2202656A
公开(公告)日：1988-09-28
申请号：GB8725112
申请日：1987-10-27
Applicant: IBM
Inventor： LO YUAN-CHANG , MOELLER DENNIS LEE , SZAREK JOHN JOSEPH
Abstract: A microcomputer system has first, low order address, memory means (17) soldered to the planar printed circuit board and can accept further memory means (18) pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.
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公开(公告)号：AU567767B2
公开(公告)日：1987-12-03
申请号：AU3409984
申请日：1984-10-10
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.
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Patent Agency Ranking
公开(公告)号：BR8406635A
公开(公告)日：1985-10-15
申请号：BR8406635
申请日：1984-12-20
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.
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公开(公告)号：ES2118792T3
公开(公告)日：1998-10-01
申请号：ES92304511
申请日：1992-05-19
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：DE69226403D1
公开(公告)日：1998-09-03
申请号：DE69226403
申请日：1992-05-19
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：CA2067602C
公开(公告)日：1998-05-05
申请号：CA2067602
申请日：1992-04-29
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , MOELLER DENNIS LEE , MATHISEN ERIC , TASHAKORI ESMAEIL , RAYMOND JONATHAN HENRY , HERNANDEZ LUIS ANTONIO
IPC: G06F13/18 , G06F13/36 , G06F13/362 , G06F13/20
Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.
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公开(公告)号：SG46499A1
公开(公告)日：1998-02-20
申请号：SG1996005249
申请日：1992-05-19
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
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