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公开(公告)号：AT304725T
公开(公告)日：2005-09-15
申请号：AT02758409
申请日：2002-07-11
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL
Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.
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公开(公告)号：DE69430529T2
公开(公告)日：2003-01-16
申请号：DE69430529
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , GUY PAILLET , TANNHOF PASCAL , GODEFROY CATHERINE
Abstract: A daisy chain circuit (600) is placed in each neuron circuit of a neural network. Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits are structured as a chain. Its main role is to distinguish between the two possible states of the neuron circuit: engaged or free and moreover to identify the first free "or ready to learn" neuron circuit in the chain. This distinction is based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network whose said input and output signals are complementary to each other. It is built around a 1-bit register (601) controlled by a store enable signal (ST) which is set active at initialization or during the learning phase when a new neuron circuit must be engaged. The input terminal of the first daisy chain circuit in the chain is connected to a first logic value, so that it is the ready to learn neuron circuit by construction after initialization. After initialization, all the registers of the chain are set to a second logic value. In the learning phase, the 1-bit register contents of the ready to learn neuron circuit is set to the said first logic value by the store enable signal, it is said "engaged". The following neuron circuit in the chain then becomes the new ready to learn neuron circuit. In addition, the daisy chain circuit is adapted to generate various control signals e.g. the control signal (RS) that allows to load the input vector components in the weight memory of only the ready to learn neuron circuit during the recognition phase.
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公开(公告)号：DE69430528D1
公开(公告)日：2002-06-06
申请号：DE69430528
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN-YVES , TANNHOF PASCAL , PAILLET GUY
Abstract: In a neural network comprised of a plurality of N neuron circuits, each having calculated the distance (D1, ... , D4) coded on p bits (D1 = d11 ... d41) between an input vector and the prototype vector stored in the weight memory thereof, there is disclosed an aggregate circuit (517) comprised of N search/sort circuits (502-1, ..., 502-4) each being placed in a neuron circuit. The search/sort circuit is adapted to determine the minimum distance among said calculated distances. Each search/sort circuit (502-1) is comprised of p elementary base units (510-11 to 510-41) connected in series and disposed in a column direction. The distance bit signals of the same bit rank are applied to said base units according a line direction. As a consequence, the base units of the aggregate circuit are organized in a matrix. The feedback signal corresponds to the signal obtained by performing an OR function in an OR gate (12.1) between all the local output signals generated by the base units of a determined line. The search process is based on the search of zeroes in the distance bit signals, from the MSB's to the LSB's. If a zero is found in a determined line, all the columns which have a one in this line are excluded from the following search. The process is continued until it remains only one distance: the searched minimum distance, that is finally available at the output of the said OR circuit. The above described search/sort circuit can be significantly improved by adjoining a latch based circuit so that the aggregate circuit is now capable to sort the remaining distances in an increasing order.
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公开(公告)号：DE60035171T2
公开(公告)日：2008-02-14
申请号：DE60035171
申请日：2000-11-14
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL , LOUIS DIDIER
Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
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公开(公告)号：DE60035171D1
公开(公告)日：2007-07-26
申请号：DE60035171
申请日：2000-11-14
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL , LOUIS DIDIER
Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
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Patent Agency Ranking
公开(公告)号：DE69430528T2
公开(公告)日：2003-01-02
申请号：DE69430528
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN-YVES , TANNHOF PASCAL , PAILLET GUY
Abstract: In a neural network comprised of a plurality of N neuron circuits, each having calculated the distance (D1, ... , D4) coded on p bits (D1 = d11 ... d41) between an input vector and the prototype vector stored in the weight memory thereof, there is disclosed an aggregate circuit (517) comprised of N search/sort circuits (502-1, ..., 502-4) each being placed in a neuron circuit. The search/sort circuit is adapted to determine the minimum distance among said calculated distances. Each search/sort circuit (502-1) is comprised of p elementary base units (510-11 to 510-41) connected in series and disposed in a column direction. The distance bit signals of the same bit rank are applied to said base units according a line direction. As a consequence, the base units of the aggregate circuit are organized in a matrix. The feedback signal corresponds to the signal obtained by performing an OR function in an OR gate (12.1) between all the local output signals generated by the base units of a determined line. The search process is based on the search of zeroes in the distance bit signals, from the MSB's to the LSB's. If a zero is found in a determined line, all the columns which have a one in this line are excluded from the following search. The process is continued until it remains only one distance: the searched minimum distance, that is finally available at the output of the said OR circuit. The above described search/sort circuit can be significantly improved by adjoining a latch based circuit so that the aggregate circuit is now capable to sort the remaining distances in an increasing order.
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27.发明专利
公开(公告)号：AU2002304860A1
公开(公告)日：2002-10-15
申请号：AU2002304860
申请日：2002-02-25
Applicant: IBM
Inventor： TANNHOF PASCAL
IPC: G06N3/063
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公开(公告)号：DE69430870D1
公开(公告)日：2002-08-01
申请号：DE69430870
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , GODEFROY CATHERINE , STEIMLE ANDRE , LOUIS DIDIER , PAILLET GUY , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and second intermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories. The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feed-back signal.
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公开(公告)号：DE68924426D1
公开(公告)日：1995-11-02
申请号：DE68924426
申请日：1989-10-26
Applicant: IBM
Inventor： MOLLIER PIERRE , NUEZ JEAN-PAUL , TANNHOF PASCAL
IPC: H03K19/013 , H03K19/086
Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.
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公开(公告)号：DE3854155D1
公开(公告)日：1995-08-17
申请号：DE3854155
申请日：1988-04-29
Applicant: IBM
Inventor： MOLLIER PIERRE , TANNHOF PASCAL
IPC: H01L27/095 , H03K5/02 , H03K19/017 , H03K19/0185 , H03K19/094 , H03K19/0952
Abstract: The present invention relates in general to fast logic circuits, and more particularly to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A typical 3 Way OR/NOR circuit includes a standard differential amplifier (DA), the first branch of which is controlled by logic input signals (E1, E3, E3). The second branch includes a current switch (T12) controlled by a reference voltage (VREF). The differential amplifier provides first and second output signals (S1, S2), simultaneous and complementary each other. The circuit further includes two push pull output buffers (PP21, PP22). First output buffer (PP21) comprises an active pull up device (FET T13) connected in series with an active pull down device (FET T20), the first circuit output signal (A1) is available at their common node or at the output terminal (21). The active pull up device (T13) is controlled by a first output signal (S1) of the differential amplifier, the active pull down device (T20) is preferably controlled by the second output signal (S2) through an intermediate source follower buffer (IB22). The second output buffer (PP22) is of similar structure, in order to supply the complementary second circuit output signal (B1). The circuit takes advantage of the fact that output signals (S1, S2) are available simultaneously and complementary each other on the outputs of the differential amplifier at output nodes (13, 14) to perform the logic function. The depicted circuit is of the dual phase type because it provides complementary circuit output signals (A1, B1). However, if only one phase of the circuit output signal (e.g. A1) is needed, the number of required devices can be reduced in the output circuit block (16). The output buffer (PP22) and the intermediate buffer (IB21) which cooperate to supply the opposite phase (B1) can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer (IB22). The gate electrode of the active pull down device (T20) is directly controlled by the second output signal (S2) complementary to the first output signal (S1) which controls the corresponding active pull up device (T13).
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