中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

56 records (took 0.023 seconds)

    24.
    发明专利
    未知

    公开(公告)号：DE19948570C2

    公开(公告)日：2001-07-26

    申请号：DE19948570

    申请日：1999-10-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G03F1/00 ,  H01L21/768 ,  H01L23/522

    Abstract: A configuration for connecting conductor tracks includes a first conductor track fabricated with a first phase mask having a first phase and a second conductor track fabricated with a second phase mask having a second phase opposite to the first phase. The first and second conductor tracks define a given metallization plane and are disposed on this given metallization plane. The first conductor track adjoins the second conductor track in a junction region such that a discontinuity is provided between the first conductor track and the second conductor track. A connecting contact is disposed above or below the given metallization plane and connects the conductor tracks in the junction region. Moving the connection above or below the metallization plane avoids phase conflicts in the junction region. A method of electrically connecting conductor tracks is also provided.

    Circuit for supplying negative voltage to word lines of semiconductor memory
    25.
    发明专利
    Circuit for supplying negative voltage to word lines of semiconductor memory 未知

    公开(公告)号：DE19961517A1

    公开(公告)日：2001-07-05

    申请号：DE19961517

    申请日：1999-12-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT

    IPC: G11C5/14 ,  G11C8/08 ,  G11C7/00

    Abstract: The circuit supplies word lines in a memory cell field of a semiconductor memory with a voltage that extends to a negative voltage value. A pump (3) is provided in the memory cell field for delivering negative voltage. The pump also supplies the word lines with negative voltage. The pump may supply negative voltage to the semiconductor body ("bulk") of a selection transistor (T) connected to the word lines and bit lines.

    Semiconductor chip separation device
    26.
    发明专利
    Semiconductor chip separation device 未知

    公开(公告)号：DE19961790C1

    公开(公告)日：2001-05-10

    申请号：DE19961790

    申请日：1999-12-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

    IPC: H01L21/301 ,  H01L23/31 ,  H01L21/78 ,  H01L23/525 ,  H01L21/304

    Abstract: The separation device separates a semiconductor chip from a semiconductor wafer having an insulation layer (3) provided with a number of metallisation planes (M0,M1,M2), in which a recess (5) is provided for reducing the thickness of the insulation layer to define a separation line. The insulation layer is provided by a silicon dioxide layer, which is provided with openings for electrical connection of the uppermost metallisation plane (M2) with the underlying metallisation plane (M1) via a connection layer (C2), together with the recess for reducing the thickness of the insulation layer.

    27.
    发明专利
    未知

    公开(公告)号：DE10124278B4

    公开(公告)日：2007-03-29

    申请号：DE10124278

    申请日：2001-05-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT

    IPC: G11C11/407 ,  G11C7/10

    Abstract: An integrated memory having a memory cell array has a control circuit for controlling a memory access for reading out or writing a data signal of one of the memory cells. The control circuit receives, for a memory access, an access command in the form of an activation command, a read command or a write command. Furthermore, the control circuit is designed and can be operated in such a way that, for a memory access, a configuration value for a CAS latency and/or a configuration value for specifying a burst access is received in a combined manner with the access command. As a result, a mode register and a corresponding programming step for programming the register can be eliminated.

    28.
    发明专利
    未知

    公开(公告)号：DE10110274B4

    公开(公告)日：2006-06-29

    申请号：DE10110274

    申请日：2001-03-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT

    IPC: G11C11/407 ,  G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

    Abstract: What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write operations in the present integrated memory, in each case at least two word lines are activated simultaneously, in each case only one bit line being selected simultaneously. Compared with conventional memory architectures, this results in a high data rate even at very high frequencies and with a variable burst length, and additionally in a comparatively low power loss.

    29.
    发明专利
    未知

    公开(公告)号：DE10123594B4

    公开(公告)日：2006-04-20

    申请号：DE10123594

    申请日：2001-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

    IPC: H01L27/085 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

    Abstract: It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.

Patent Agency Ranking