公开(公告)号：DE19838108B4

公开(公告)日：2005-05-25

申请号：DE19838108

申请日：1998-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

公开(公告)号：DE102004007208B3

公开(公告)日：2005-05-25

申请号：DE102004007208

申请日：2004-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H03K17/082 ,  H03K17/30 ,  H03K17/695 ,  H03K17/687

Abstract: The circuit arrangement has connection terminals (K1,K2) for applying supply voltage, a load transistor (M) with a control connection (G) and first and second load connections (D,S) for connecting a load (Z) to the supply voltage, a drive connection (IN) for applying a drive signal to the control connection, a voltage limiter circuit (10) between one load connection and the drive connection and a deactivation circuit (20) for deactivating the voltage limiter circuit depending on the supply voltage. An independent claim is also included for a method of driving a load transistor.

公开(公告)号：DE10344038A1

公开(公告)日：2005-04-14

申请号：DE10344038

申请日：2003-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L27/098 ,  H01L29/06 ,  H01L29/808 ,  H01L21/337

Abstract: A field effect transistor junction (JFET) with a semiconductor body (2, 3) of first (n) conduction type has a first main surface and second main surface opposite to it, a drain electrode (D) with drain zones, a source electrode (S) with source zones, a gate electrode (G) between the source and drain zones, and a channel zone. The source electrode also has regions of a different conduction type, so that a pn-transition is obtained between the source and drain electrodes.

公开(公告)号：DE19535985B4

公开(公告)日：2005-02-17

申请号：DE19535985

申请日：1995-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H03K17/0412 ,  H03K17/06 ,  H03K17/689

公开(公告)号：DE10325748A1

公开(公告)日：2005-01-05

申请号：DE10325748

申请日：2003-06-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLMEROTH ARMIN ,  TIHANYI JENOE ,  DEBOY GERALD ,  ZVEREV ILIA ,  PFIRSCH FRANK

IPC: H01L29/24 ,  H01L29/808

Abstract: Junction field effect transistor comprises p+> -conducting regions (4, 6) lying next to a control electrode (G) and extending together with and parallel to a drift zone (3) between electrodes in a semiconductor body (1).

公开(公告)号：DE10313712A1

公开(公告)日：2004-10-21

申请号：DE10313712

申请日：2003-03-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor component has a semiconductor body (100) with first and second semiconductor layers (110;112), with a first connection zone (20) in the second semiconductor layer (112) and with a channel zone (30) formed between the first connection zone and the drift zone (40). A first control electrode (60) is insulated against the semiconductor body (100) and is adjacent to the channel zone. At least a second control electrode (70) extends from the front face (102) through the second semiconductor layer (112) up to the first semiconductor layer (110) and is insulated against the semiconductor body.

公开(公告)号：DE10301939A1

公开(公告)日：2004-09-09

申请号：DE10301939

申请日：2003-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: FET source and drain of first conductivity are located in semiconductor layer (2), while gates (6,7) are insulated from source and drain zone by oxide insulating layer (4,5). Gates are of same semiconductor material as source and/or drain zone, insulated from them by oxide layer in trench.Preferably gate material is monocrystalline silicon and is located between pair of trenches filled with oxide layer. Source and drain zone and gates are formed by semiconductor layer of first conductivity on semiconductor substrate of second conductivity.

公开(公告)号：DE10301693A1

公开(公告)日：2004-08-05

申请号：DE10301693

申请日：2003-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L27/07 ,  H01L29/06 ,  H01L29/78 ,  H03K17/0814 ,  H03K17/16 ,  H03K17/687

Abstract: A MOSFET circuit having reduced voltage output oscillations through a switch-off device as the current falls to zero comprises two MOS transistors (T1,T2), the second having fewer cells than the first, with their source/drain regions in parallel between a voltage source (+U) and a voltage element (preferably a zener diode) between their gates.

公开(公告)号：DE10245050A1

公开(公告)日：2004-04-08

申请号：DE10245050

申请日：2002-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L29/417 ,  H01L29/739 ,  H01L29/74

Abstract: A semiconductor element has a first connection zone (FCZ) (60) for a first mode of conductivity (MOC) with a drift zone (DZ) (40). A semiconductor zone (50) for a second MOC fits between the FCZ and the DZ. A connection electrode (90) makes contact with a second connection zone (SCZ) (20) for a second MOC. The DZ fits between the SCZ and a channel zone insulated against a control electrode (70).

公开(公告)号：DE59711273D1

公开(公告)日：2004-03-11

申请号：DE59711273

申请日：1997-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE

IPC: H01L23/367 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A field effect-controllable vertical semiconductor device consists of a semiconductor body having first conductivity type source (3, 3') and drain (2, 8) zones, a gate electrode (4) insulated from the semiconductor body (1) by a gate oxide (14), and a first conductivity type bulk region (10). The novelty is that the source connection (S) is located on the wafer back face (12) and preferably fixed on a copper heat sink (9), while the drain and gate connections (D, G) are located on the wafer front face (11). Also claimed is a process for producing the above device by (i) depositing the various interior zone (5) epitaxial layers on the bulk region (10) of a semiconductor body (1); (ii) epitaxially depositing the source/drain zones (2, 3) on the interior zone (5); (iii) structuring the wafer front face (11) and ion implanting the heavily doped source region (3'); (iv) re-structuring the wafer front face (11) and anisotropically etching the inter-cell zones (6); (v) using the etching mask for ion implantation of the channel zones (7); (vi) using the etching mask for thermally applying a thin SiO2 layer as gate oxide (14) on the trench walls of the inter-cell zones (6), filling the inter-cell zones (6) with polysilicon as gate material, etching away excess polysilicon from the inter-cell zones (6) and filling the inter-cell zones (6) with SiO2; (vii) re-structuring the wafer front face (11) and anisotropically etching trenches (13) in the region of the source zones (3, 3') down to the depth of the bulk zone (10); (viii) applying a thin oxide onto the walls of these further trenches (13) and filling with conductive material; (ix) metallising the entire wafer back face (12) to form the source connection (S); metallising the wafer front face (11) at corresponding contacts to form the drain and gate connections (D, G) isolated from one another by an intermediate oxide (15); and (x) conductively fixing the source connection (S) to the heat sink (9) by a solder.