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    JUNCTION INSULATED LATERAL MOSFET FOR HIGH/LOW SIDE SWITCHES
    1.
    发明申请
    JUNCTION INSULATED LATERAL MOSFET FOR HIGH/LOW SIDE SWITCHES 审中-公开
    结隔离横向MOSFET用于高/低压侧开关

    公开(公告)号：WO0072360A3

    公开(公告)日：2001-07-19

    申请号：PCT/DE0001492

    申请日：2000-05-12

    Applicant: INFINEON TECHNOLOGIES AG ,  TIHANYI JENOE

    Inventor： TIHANYI JENOE

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/7833 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1033

    Abstract: The invention relates to a junction insulated lateral MOSFET for high/low side switches. A p-conductive wall (4) between an n- conductive source zone (2) and an n-conductive drain zone (3), together with the source zone (2) and drain zone (3), extend to a p-conductive substrate (1). The source zone (2) and the drain zone (3) are surrounded by a p-conductive area (5).

    Abstract translation: 本发明涉及一种用于高/低侧开关一个结隔离横向MOSFET，其中的n型源区（2）和n型漏极区（3）p型导电壁之间（4- ）（与源区2）和漏区（3）一起，以在p型衬底（1），其中，所述源极区（2）和漏区（3）由p 导电区（5）包围。

    CONTROLLABLE SEMICONDUCTOR SWITCHING ELEMENT THAT BLOCKS IN BOTH DIRECTIONS
    3.
    发明申请
    CONTROLLABLE SEMICONDUCTOR SWITCHING ELEMENT THAT BLOCKS IN BOTH DIRECTIONS 审中-公开
    可控对两个方向均LOCK相关半导体电路元件

    公开(公告)号：WO0143200B1

    公开(公告)日：2001-11-08

    申请号：PCT/EP0007603

    申请日：2000-08-04

    Applicant: INFINEON TECHNOLOGIES AG ,  TIHANYI JENOE

    Inventor： TIHANYI JENOE

    IPC: H01L21/336 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L21/331

    CPC classification number: H01L29/7813 ,  H01L29/04 ,  H01L29/086 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7802

    Abstract: The invention relates to a controllable semiconductor switching element that blocks in both directions. Said semiconductor switching element comprises a first conduction region (12) and a second conduction region (14, 16) of a first type of conductivity (n, n+), a blocking region (18; 58) of a second type of conductivity (p) which is arranged between the first and second conduction regions (12, 14, 16), and a control electrode (20) which is arranged opposite the blocking region (18; 58) in an insulated manner. A recombination region is configured in the blocking region (18) and is comprised of a material that promotes a recombination of charge carriers of the first and second type of conductivity.

    Abstract translation: 本发明涉及一种在具有第一导电区（12）和第一导电类型的第二管道区域（14，16）的两个方向半导体开关元件的可控锁定（N，N +），一个在第一和第二线区域之间（12，14，16） 具有布置控制电极（20）布置在第二导电类型（p）的受限制的区域（18 ;; 58）和从所述阻挡区域（58 18）绝缘。 在限制区域（18）的再结合区上形成，它由第一和第二导电类型的促销材料的载流子复合的。

    IMPLANTATION MASK FOR HIGH ENERGY ION IMPLANTATION
    5.
    发明申请
    IMPLANTATION MASK FOR HIGH ENERGY ION IMPLANTATION 审中-公开
    注入掩模高能离子注入

    公开(公告)号：WO0161735A3

    公开(公告)日：2002-07-18

    申请号：PCT/DE0100596

    申请日：2001-02-15

    Applicant: INFINEON TECHNOLOGIES AG ,  LEHMANN VOLKER ,  RUEB MICHAEL ,  TIHANYI JENOE

    Inventor： LEHMANN VOLKER ,  RUEB MICHAEL ,  TIHANYI JENOE

    IPC: H01L21/266 ,  H01L29/06 ,  H01L23/544

    CPC classification number: H01L29/0634 ,  H01L21/266

    Abstract: The invention relates to a re-usable implantation mask (5), preferably made of silicon, comprising specially structured trenches and holes(2 or 3), which is provided directly or at a distance from a device wafer (7). The invention also relates to a method for adjusting a further processing plane on an implantation plane in a semiconductor wafer (7) fitted with one such implementation mask.

    Abstract translation: 本发明涉及一种可重复使用的注入掩模（5）配有特定图案的沟槽和孔制成优选硅（2或3），其直接或在器件晶片（7），以及用于在注入电平调整一个进一步的处理面的方法的距离设置 一个具有这样的注入掩模的半导体晶片（7）处理。

    SOURCE-DOWN POWER TRANSISTOR
    6.
    发明申请
    SOURCE-DOWN POWER TRANSISTOR 审中-公开
    SOURCE DOWN功率晶体管

    公开(公告)号：WO0072359A3

    公开(公告)日：2001-09-07

    申请号：PCT/DE0001459

    申请日：2000-05-10

    Applicant: INFINEON TECHNOLOGIES AG ,  TIHANYI JENOE

    Inventor： TIHANYI JENOE

    IPC: H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L29/7834 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4236

    Abstract: The invention relates to a source-down power transistor in which narrow trenches (11) are provided between a source column (9) and a drain column (10). Said trenches are filled with insulated polysilicon (14). Inversion channels form on the lateral walls of the trenches in the instance of a positive drain voltage and a positive gate voltage. A current that can be controlled by the gate voltage flows inside said inversion channels.

    Abstract translation: 本发明涉及一种源极向下功率晶体管，其中源极柱（9）和填充有上，其侧壁的绝缘多晶硅（14）的漏极 - 塔（10）窄沟槽（11）被设置之间， 具有正漏极电压和栅极电压正反转通道形成其中通过栅极电压电流流过可控的。

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