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    Power management apparatus and method
    21.
    发明专利
    Power management apparatus and method 未知

    公开(公告)号：AU1355997A

    公开(公告)日：1997-07-28

    申请号：AU1355997

    申请日：1996-12-27

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

    IPC: G06F1/32

    Abstract: A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

    Slow memory refresh in a computer with a limited supply of power
    23.
    发明专利
    Slow memory refresh in a computer with a limited supply of power 未知

    公开(公告)号：GB2264799B

    公开(公告)日：1994-11-16

    申请号：GB9305800

    申请日：1993-03-19

    Applicant: INTEL CORP

    Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

    IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

    Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

    27.
    发明专利
    未知

    公开(公告)号：DE19782133B4

    公开(公告)日：2004-08-19

    申请号：DE19782133

    申请日：1997-09-29

    Applicant: INTEL CORP

    Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

    IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40 ,  G06F15/17

    Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

    28.
    发明专利
    未知

    公开(公告)号：DE19681716T1

    公开(公告)日：1998-11-26

    申请号：DE19681716

    申请日：1996-12-27

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

    IPC: G06F1/32 ,  G06F13/00

    Abstract: A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

    Method and apparatus for docking and undocking a notebook computer
    29.
    发明专利
    Method and apparatus for docking and undocking a notebook computer 未知

    公开(公告)号：AU4739997A

    公开(公告)日：1998-06-10

    申请号：AU4739997

    申请日：1997-09-29

    Applicant: INTEL CORP

    Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

    IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40 ,  H01J3/00

    Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

    Transparent system interrupts with automated halt state restart
    30.
    发明专利
    Transparent system interrupts with automated halt state restart 未知

    公开(公告)号：GB2259167B

    公开(公告)日：1995-01-25

    申请号：GB9217850

    申请日：1992-08-21

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES P ,  NGUYEN CAU

    IPC: G06F9/46 ,  G06F9/48

    Abstract: A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of interruption and a halt indicator indicating the CPU was interrupted from a halt state. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The halt state indicator is set by the added interrupt of the CPU is in a halt state at the time of interruption. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The Halt instruction is re-executed by the RESUME instruction if the halt state indicator remains set at the time of restoration. As a result, a system integrator or OEM may provide transparent system level interrupts with automated halt state restart that will operate reliably in any operating environment, and be relieved of the burden of managing halt state restart.

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