公开(公告)号：US09141454B2

公开(公告)日：2015-09-22

申请号：US13728217

申请日：2012-12-27

Applicant: Intel Corporation

Inventor： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/006 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793

Abstract: Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.

Abstract translation: 公开了用于信令软件可恢复错误的发明的实施例。 在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。 第一个单位是检测毒物的错误。 可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。 第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

公开(公告)号：US12013790B2

公开(公告)日：2024-06-18

申请号：US18321490

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/06 ,  G06F12/1081

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/1081 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US20230418762A1

公开(公告)日：2023-12-28

申请号：US18321490

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/06 ,  G06F12/1081

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/1081 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US20230409197A1

公开(公告)日：2023-12-21

申请号：US18239363

申请日：2023-08-29

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Ashok Raj ,  Ned Smith ,  Weigang Li ,  Junyuan Wang ,  Xin Zeng ,  Brian Will ,  Zijuan Fan ,  Michael E. Kounavis ,  Qianjun Xie ,  Yuan Wang ,  Yao Huo

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673

Abstract: An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (JO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

公开(公告)号：US11698866B2

公开(公告)日：2023-07-11

申请号：US16651786

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/06 ,  G06F12/1081

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/1081 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US20230103000A1

公开(公告)日：2023-03-30

申请号：US17485386

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rupin Vakharwala ,  Prashant Sethi ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  David J. Harriman ,  Utkarsh Y. Kakaiya ,  Vinay Raghav ,  Ashok Raj ,  Siva Bhanu Krishna Boga

IPC: G06F12/1027 ,  G06F12/0802 ,  G06F13/42

Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer. The second interconnect is in the only path between the device and the system memory.

公开(公告)号：US20210191753A1

公开(公告)日：2021-06-24

申请号：US16723691

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Jacob Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F9/48 ,  G06F9/54

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

公开(公告)号：US10474596B2

公开(公告)日：2019-11-12

申请号：US14749893

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  John G. Holm ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: G06F13/24 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228

Abstract: In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.

公开(公告)号：US20190196988A1

公开(公告)日：2019-06-27

申请号：US15855798

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Omid Azizi ,  Chandan Egbert ,  Amin Firoozshahian ,  David Christopher Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Ashok Raj ,  Alexandre Solomatnikov ,  Stephen Van Doren

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F2213/24

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

公开(公告)号：US10319458B2

公开(公告)日：2019-06-11

申请号：US15457326

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/52 ,  G11C29/04 ,  G11C29/44 ,  G11C13/00

Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.