公开(公告)号：US20240222301A1

公开(公告)日：2024-07-04

申请号：US18147497

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Sairam Agraharam ,  Ashay Dani ,  Eric J. M. Moret ,  Tarek Ibrahim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L2224/10122 ,  H01L2224/11011 ,  H01L2924/143 ,  H01L2924/186

Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.

公开(公告)号：US20240222259A1

公开(公告)日：2024-07-04

申请号：US18147535

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Xiyu Hu ,  Rhonda Jack ,  Catherine Mau ,  Hongxia Feng ,  Xiao Liu ,  Wei Wei ,  Srinivas Pietambaram ,  Gang Duan ,  Xiaoying Guo ,  Dingying Xu ,  Kyle Arrington ,  Ziyin Lin ,  Hiroki Tanaka ,  Leonel Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/16

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.

公开(公告)号：US20240222136A1

公开(公告)日：2024-07-04

申请号：US18091188

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ashay A. Dani ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Wei Wei ,  Ziyin Lin

IPC: H01L21/321 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/7684

Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.

公开(公告)号：US20240219659A1

公开(公告)日：2024-07-04

申请号：US18089871

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4239 ,  H01Q1/2283

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

公开(公告)号：US20240186250A1

公开(公告)日：2024-06-06

申请号：US18061188

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Suddhasattwa Nad ,  Gang Duan ,  Haobo Chen ,  Hiroki Tanaka

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386

Abstract: A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.

公开(公告)号：US20240162157A1

公开(公告)日：2024-05-16

申请号：US17988051

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Aleksandar Aleksov ,  Srinivas V. Pietambaram ,  Haobo Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L25/0655

Abstract: A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.

公开(公告)号：US11923312B2

公开(公告)日：2024-03-05

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Srinivas Pietambaram ,  Jesse Jones ,  Yosuke Kanaoka ,  Hongxia Feng ,  Dingying Xu ,  Rahul Manepalli ,  Sameer Paital ,  Kristof Darmawikarta ,  Yonggang Li ,  Meizi Jiao ,  Chong Zhang ,  Matthew Tingey ,  Jung Kyu Han ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.