公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC: H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.