公开(公告)号：US20240178207A1

公开(公告)日：2024-05-30

申请号：US18059089

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L25/167 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/428 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/08 ,  H01L2224/08121 ,  H01L2224/08225 ,  H01L2924/1903

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes through-glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical pathway through the interposer.

公开(公告)号：US20240162158A1

公开(公告)日：2024-05-16

申请号：US18055605

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Sashi Shekhar Kandanur ,  Ravindranath Vithal Mahajan ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/538 ,  B81B1/00 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B81B1/002 ,  H01L23/3121 ,  H01L23/467 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5384 ,  B81B2201/0214 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first IC die or the second IC die.

公开(公告)号：US20240113029A1

公开(公告)日：2024-04-04

申请号：US17957783

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Hiroki Tanaka ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/13 ,  H01L23/15 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/16 ,  H01L24/16

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

公开(公告)号：US20240105655A1

公开(公告)日：2024-03-28

申请号：US17934721

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. In some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. In some embodiments, the liner also may be on side surfaces of the interconnect.

公开(公告)号：US11942334B2

公开(公告)日：2024-03-26

申请号：US16231181

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Suddhasattwa Nad ,  Kristof Kuwawi Darmawikarta ,  Vahidreza Parichehreh ,  Veronica Aleman Strong ,  Xiaoying Guo

IPC: H05K1/02 ,  H01L21/027 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L21/4846 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H05K1/0218 ,  H01L2224/16225

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

公开(公告)号：US20240071933A1

公开(公告)日：2024-02-29

申请号：US17823602

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/16148 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (IC) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second IC die in the organic dielectric material, the second IC die conductively coupling a pair of first IC dies in the plurality of first IC dies of the first layer; and a package substrate coupled to the second side of the first layer. The second IC die is coupled to the pair of first IC dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first IC dies comprises TSVs conductively coupling circuits in the first IC dies with the interconnects.

公开(公告)号：US11817349B2

公开(公告)日：2023-11-14

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76885 ,  H01L21/7685 ,  H01L21/76834 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/53238 ,  H01L21/32134

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US20220399150A1

公开(公告)日：2022-12-15

申请号：US17348580

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Matthew Tingey ,  Ravindranath Mahajan ,  Srinivas Pietambaram

IPC: H01F27/28 ,  H01L25/18 ,  H01L23/498 ,  H01F27/32

Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

公开(公告)号：US20210296225A1

公开(公告)日：2021-09-23

申请号：US16827085

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Ravindranath Mahajan ,  Brandon Marin ,  Jeremy Ecton ,  Mohammad Mamunar Rahman

IPC: H01L23/50 ,  H01L29/06

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

公开(公告)号：US20250149455A1

公开(公告)日：2025-05-08

申请号：US18503459

申请日：2023-11-07

Applicant: Intel Corporation

Inventor： Nicholas Haehn ,  Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.