公开(公告)号：US20210036618A1

公开(公告)日：2021-02-04

申请号：US16642268

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： WILLIAM J. Lambert ,  Kaladhar Radhakrishnan ,  Beomseok Choi ,  Krishna Bharath ,  Michael J. Hill

IPC: H02M3/158 ,  G01R19/165 ,  G05F1/46 ,  H01F21/02

Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.

公开(公告)号：US20180101207A1

公开(公告)日：2018-04-12

申请号：US15695947

申请日：2017-09-05

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M1/14 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

公开(公告)号：US12288750B2

公开(公告)日：2025-04-29

申请号：US17485208

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

公开(公告)号：US11955426B2

公开(公告)日：2024-04-09

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6672

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US20240063183A1

公开(公告)日：2024-02-22

申请号：US17820982

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Anne Augustine ,  Beomseok Choi ,  Kimin Jun ,  Omkar G. Karhade ,  Shawna M. Liff ,  Julien Sebot ,  Johanna M. Swan ,  Krishna Vasanth Valavala

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L24/08 ,  H01L24/16 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/80 ,  H01L23/481 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/37001 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.

公开(公告)号：US11462463B2

公开(公告)日：2022-10-04

申请号：US16145059

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01F27/24 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US20200098621A1

公开(公告)日：2020-03-26

申请号：US16140398

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L21/768

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20200066634A1

公开(公告)日：2020-02-27

申请号：US16107757

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/66

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US20200006292A1

公开(公告)日：2020-01-02

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US20190279973A1

公开(公告)日：2019-09-12

申请号：US16426939

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadla ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01L25/16 ,  H01L23/64 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01F17/00 ,  H01L23/00

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material: a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.