公开(公告)号：US20230298126A1

公开(公告)日：2023-09-21

申请号：US17699059

申请日：2022-03-18

Applicant: INTEL CORPORATION

Inventor： Sven Woop ,  Carsten Benthin ,  Prasoonkumar Surti ,  Joshua Barczak ,  Abhishek R. Appu ,  Pawel Majewski

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

Abstract: Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

公开(公告)号：US11755501B2

公开(公告)日：2023-09-12

申请号：US17212503

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Elmoustapha Ould-Ahmed-Vall ,  Michael Macpherson ,  Aravindh V. Anantaraman ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Varghese George ,  Abhishek Appu ,  Prasoonkumar Surti

IPC: G06F13/16 ,  G06F9/50 ,  G06T1/60 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F13/1605 ,  G06F9/3004 ,  G06F9/3887 ,  G06F9/5016 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

公开(公告)号：US11748841B2

公开(公告)日：2023-09-05

申请号：US17871781

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06N3/063 ,  G06F9/46 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06N3/044

CPC classification number: G06T1/20 ,  G06F9/46 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/044 ,  G06N3/084

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.

公开(公告)号：US11688122B2

公开(公告)日：2023-06-27

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20230109990A1

公开(公告)日：2023-04-13

申请号：US17496467

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Altug Koker ,  Aditya Navale ,  Prasoonkumar Surti ,  Ankur Shah ,  Joydeep Ray ,  Naveen Matam

IPC: G06T1/20

Abstract: One embodiment provides a graphics processor including an active base die including a fabric interconnect and a chiplet including a switched fabric, wherein the chiplet couples with the active base die via an array of interconnect structures, the array of interconnect structures couple the fabric interconnect with the switched fabric, and the chiplet includes a first modular interconnect configured to couple a block of graphics processing resources to the switched fabric and a second modular interconnect configured to couple a memory subsystem with the switched fabric and the block of graphics processing resources, the memory interconnect including a set of memory controllers and a set of physical interfaces.

公开(公告)号：US11620256B2

公开(公告)日：2023-04-04

申请号：US17732308

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/08 ,  G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06T15/06 ,  G06N3/08

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US11557064B2

公开(公告)日：2023-01-17

申请号：US16750819

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Pradeep Ramani ,  Rama Harihara ,  Jerin C. Justin ,  Jing Huang ,  Xiaoming Cui ,  Timothy B. Costa ,  Ting Gong ,  Elmoustapha Ould-ahmed-vall ,  Kumar Balasubramanian ,  Anil Thomas ,  Oguz H. Elibol ,  Jayaram Bobba ,  Guozhong Zhuang ,  Bhavani Subramanian ,  Gokce Keskin ,  Chandrasekaran Sakthivel ,  Rajesh Poornachandran

IPC: G06T15/00 ,  G06T9/00 ,  G06F12/02

Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.

公开(公告)号：US20220414977A1

公开(公告)日：2022-12-29

申请号：US17357423

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Ronald Silvas ,  Karol A. Szerszen

IPC: G06T15/50 ,  G06T15/80 ,  G06T15/04 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20

Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.

公开(公告)号：US20220414967A1

公开(公告)日：2022-12-29

申请号：US17357403

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Jorge Garcia Pabon ,  John Gierach

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/10

Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.

公开(公告)号：US11494968B2

公开(公告)日：2022-11-08

申请号：US17322677

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.