公开(公告)号：US20210083117A1

公开(公告)日：2021-03-18

申请号：US16642335

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

公开(公告)号：US20210074704A1

公开(公告)日：2021-03-11

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US10937665B2

公开(公告)日：2021-03-02

申请号：US16327713

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Harold W. Kennel ,  Patrick Morrow ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L21/322 ,  H01L21/265 ,  H01L21/768 ,  H01L21/38 ,  H01L21/70 ,  H01L23/26

Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

公开(公告)号：US20200335501A1

公开(公告)日：2020-10-22

申请号：US16957664

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/06 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US20200227556A1

公开(公告)日：2020-07-16

申请号：US16637215

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/8234

Abstract: Techniques and mechanisms for imposing stress on transistors using an insulator. In an embodiment, an integrated circuit device includes a fin structure on a semiconductor substrate, wherein respective structures of two transistors are variously in or on the fin structure. A recess of the IC device, located in a region between the two transistors, extends at least partially through the fin structure. An insulator in the recess imposes stresses on respective channel regions of the two transistors. In another embodiment, compressive stresses or tensile stresses are imposed on the transistors with both the insulator and a buffer layer under the fin structure.

公开(公告)号：US20200152750A1

公开(公告)日：2020-05-14

申请号：US16487077

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Glenn A. Glass ,  Anand S. Murthy ,  Rishabh Mehandru

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

公开(公告)号：US20200098756A1

公开(公告)日：2020-03-26

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

公开(公告)号：US10529827B2

公开(公告)日：2020-01-07

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Paul B. Fischer ,  Aaron D. Lilak ,  Stephen M. Cea

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

公开(公告)号：US20190096917A1

公开(公告)日：2019-03-28

申请号：US16082260

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Nathan D. Jack

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/00 ,  H01L21/762 ,  H01L29/786

Abstract: Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.

公开(公告)号：US20180323195A1

公开(公告)日：2018-11-08

申请号：US15773325

申请日：2015-12-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Roza Kotlyar ,  Stephen M. Cea ,  Patrick H. Keys

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.