公开(公告)号：WO2016048499A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/046064

申请日：2015-08-20

Applicant: INTEL CORPORATION

Inventor： FARRELL, Robert L. ,  SURTI, Prasoonkumar ,  RANGANATHAN, Vasanth ,  SZERSZEN, Karol A.

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T5/002 ,  G06T9/00 ,  G06T11/40

Abstract: By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.

Abstract translation: 通过以独立于样本数量的方式打包深度数据，使得存储器带宽相同，而不管样本数量如何，可以使用每像素更多的采样数，而不会不利地影响缓冲器成本。 在一些实施例中，可以通过在像素域中操作来增加第一级深度测试中每个时钟的像素数量，而先前的解决方案在采样级别下运行。

公开(公告)号：WO2014204703A1

公开(公告)日：2014-12-24

申请号：PCT/US2014/041622

申请日：2014-06-10

Applicant: INTEL CORPORATION ,  SURTI, Prasoonkumar ,  AKENINE-MOLLER, Tomas G. ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl J. ,  NILSSON, Jim K.

Inventor： SURTI, Prasoonkumar ,  AKENINE-MOLLER, Tomas G. ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl J. ,  NILSSON, Jim K.

IPC: G06T1/00 ,  G06T9/00

CPC classification number: G06T1/60 ,  G06T9/005 ,  G06T11/40

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.

Abstract translation: 描述与图形渲染相关的技术，包括通过使用索引子集来压缩和/或解压缩图形数据的技术。

公开(公告)号：WO2014204692A1

公开(公告)日：2014-12-24

申请号：PCT/US2014/041481

申请日：2014-06-09

Applicant: INTEL CORPORATION ,  AKENINE-MOLLER, Tomas G. ,  NILSSON, Jim K. ,  SURTI, Prasoonkumar ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl J.

Inventor： AKENINE-MOLLER, Tomas G. ,  NILSSON, Jim K. ,  SURTI, Prasoonkumar ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl J.

IPC: G06T9/00 ,  G06T1/00

CPC classification number: G06T1/60 ,  G06K9/4652 ,  G06K2009/4666 ,  G06T7/90 ,  G06T9/00 ,  G06T11/00 ,  G06T2200/28 ,  G06T2207/20021

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.

Abstract translation: 描述了与图形渲染相关的技术，包括通过使用像素区域位值来压缩和/或解压缩图形数据的技术。

公开(公告)号：WO2023009181A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/021968

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： HOEKSTRA, Eric ,  SURTI, Prasoonkumar ,  APPU, Abhishek R. ,  MAIYURAN, Subramaniam ,  BHIRAVABHATLA, Kalyan

IPC: G06T1/20 ,  G06T3/40 ,  G06T7/66

Abstract: Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.

公开(公告)号：WO2020190813A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022851

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： APPU, Abhishek ,  STRIRAMASSARMA, Lakshminarayanan ,  KOKER, Altug ,  COLEMAN, Sean ,  GEORGE, Varghese ,  HUNTER, JR., Arthur ,  INSKO, Brent ,  JANUS, Scott ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0886 ,  G06F12/0862 ,  G06F9/38

Abstract: Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

公开(公告)号：WO2020190811A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022849

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  STRIRAMASSARMA, Lakshminarayanan ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  APPU, Abhishek R. ,  COLEMAN, Sean ,  GEORGE, Varghese ,  K, Pattabhiraman ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  OULD-AHMED-VALL, ElMoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  S, Jayakrishna P ,  SURTI, Prasoonkumar

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：WO2020190807A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022845

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： SURTI, Prasoonkumar ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin ,  APPU, Abhishek ,  GEORGE, Varghese ,  KOKER, Altug ,  MACPHERSON, Mike ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  STRIRAMASSARMA, Lakshminarayanan ,  KIM, SungYe

IPC: G06F9/30

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.

公开(公告)号：WO2020190429A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017897

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

Inventor： VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

IPC: G06F12/0862 ,  G06F12/0897 ,  G06F12/0888 ,  G06F9/38

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：WO2020068311A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/047480

申请日：2019-08-21

Applicant: INTEL CORPORATION

Inventor： DESAI, Kinchit ,  JAHAGIRDAR, Sanjeev ,  SURTI, Prasoonkumar ,  RAY, Joydeep

IPC: G06N3/063 ,  G06N3/08 ,  G06F1/3206 ,  G06F1/3234 ,  G06N3/04

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：WO2018057109A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/043950

申请日：2017-07-26

Applicant: INTEL CORPORATION

Inventor： AKENINE-MOLLER, Tomas, G. ,  SURTI, Prasoonkumar ,  KOKER, Altug ,  PUFFER, David ,  NILSSON, Jim

IPC: G06T1/60 ,  G06T1/20 ,  G06T9/00

CPC classification number: G06F12/0875 ,  G06F3/0655 ,  G06F12/0207 ,  G06F12/084 ,  G06F12/0842 ,  G06F17/22 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.

Abstract translation: 这里描述了几个实施例，其结合自适应和动态压缩来提供增强数据缓存，以在GPU的输入和输出期间增加存储效率并降低数据的传输带宽。 本文描述的技术可以减少访问片外存储器的需要，导致GPU操作的改进的性能和降低的功率。 一个实施例提供了一种包括着色引擎的图形处理装置; 一个或多个高速缓存存储器 高速缓存控制逻辑，用于控制一个或多个高速缓存存储器中的至少一个; 以及与所述一个或多个高速缓冲存储器耦合的编解码器单元，所述编解码器单元可配置为在存储到所述一个或多个高速缓冲存储器或从所述一个或多个高速缓冲存储器逐出时执行只读表面数据的无损压缩。