公开(公告)号：WO2020190805A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022843

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  OULD-AHMED-VALL, ElMoustapha ,  ANDREI, Valentin ,  GALOPPO VON BORRIES, Nicolas ,  GEORGE, Varghese ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  RAY, Joydeep ,  STRIRAMASSARMA, Lakshminarayanan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  PUFFER, David ,  VALERIO, James ,  SHAH, Ankur N.

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F16/27 ,  G06F12/0866 ,  G06F16/2453

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2022093456A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/052090

申请日：2021-09-24

Applicant: INTEL CORPORATION

Inventor： ZAGE, David ,  JANUS, Scott ,  SMITH, Ned M. ,  KRISHNAN, Vidhya ,  CHHABRA, Siddhartha ,  POORNACHANDRAN, Rajesh ,  LEVY, Tomer ,  CARRENO, Julien ,  SHAH, Ankur ,  SILVAS, Ronald ,  ANANTARAMAN, Aravindh ,  PUFFER, David ,  SHANBHOGUE, Vedvyas ,  COWPERTHWAITE, David ,  NAVALE, Aditya ,  BEN-SHALOM, Omer ,  NAYSHTUT, Alex ,  RUAN, Xiaoyu

IPC: G06F21/72 ,  G06F21/62 ,  G06F21/10 ,  H04L9/08 ,  H04L9/32 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

公开(公告)号：WO2020190806A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022844

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  GEORGE, Varghese ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  APPU, Abhishek R. ,  COORAY, Niran ,  GALOPPO VON BORRIES, Nicolas ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  OULD-AHMED-VALL, ElMoustapha ,  PUFFER, David ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SHAH, Ankur N. ,  STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar ,  TANGRI, Saurabh

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30

Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

公开(公告)号：WO2018057109A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/043950

申请日：2017-07-26

Applicant: INTEL CORPORATION

Inventor： AKENINE-MOLLER, Tomas, G. ,  SURTI, Prasoonkumar ,  KOKER, Altug ,  PUFFER, David ,  NILSSON, Jim

IPC: G06T1/60 ,  G06T1/20 ,  G06T9/00

CPC classification number: G06F12/0875 ,  G06F3/0655 ,  G06F12/0207 ,  G06F12/084 ,  G06F12/0842 ,  G06F17/22 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.

Abstract translation: 这里描述了几个实施例，其结合自适应和动态压缩来提供增强数据缓存，以在GPU的输入和输出期间增加存储效率并降低数据的传输带宽。 本文描述的技术可以减少访问片外存储器的需要，导致GPU操作的改进的性能和降低的功率。 一个实施例提供了一种包括着色引擎的图形处理装置; 一个或多个高速缓存存储器 高速缓存控制逻辑，用于控制一个或多个高速缓存存储器中的至少一个; 以及与所述一个或多个高速缓冲存储器耦合的编解码器单元，所述编解码器单元可配置为在存储到所述一个或多个高速缓冲存储器或从所述一个或多个高速缓冲存储器逐出时执行只读表面数据的无损压缩。

公开(公告)号：WO2014070255A1

公开(公告)日：2014-05-08

申请号：PCT/US2013/048031

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： GARCIA, Guadalupe J. ,  JAGANNATHAN, Lakshminarayan K. ,  PUFFER, David

IPC: G06F1/08 ,  G06F1/26

CPC classification number: G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: In many cases, processors may change frequency sufficiently often to result in significant performance and power consumption losses. These performance and power consumption losses may be mitigated by changing the frequency using a squashing technique rather than using a phase locked loop technique. The squashing technique involves simply eliminated clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases.

Abstract translation: 在许多情况下，处理器可能会频繁地频繁地改变频率，从而导致显着的性能和功耗损失。 这些性能和功耗损失可以通过使用压扁技术改变频率而不是使用锁相环技术来减轻。 挤压技术简单地消除了时钟脉冲以降低频率。 这可以更快地完成，在某些情况下导致更少的开销。

公开(公告)号：WO2013003255A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/043938

申请日：2012-06-25

Applicant: INTEL CORPORATION ,  KABURLASOS, Nikos ,  SAMSON, Eric C. ,  PUFFER, David ,  JAGANNATHAN, Lakshminarayan

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric C. ,  PUFFER, David ,  JAGANNATHAN, Lakshminarayan

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/08 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.

Abstract translation: 处理器可以在第一时间间隔的第一频率级别操作。 处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。 然后，处理器在第二时间间隔后自动从休眠状态转换到第一频率级。 因此，处理器可以以降低的功率消耗和更高的性能来操作。

公开(公告)号：EP4325371A2

公开(公告)日：2024-02-21

申请号：EP23217515.8

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： COORAY, Niranjan L. ,  APPU, Abhishek R. ,  KOKER, Altug ,  RAY, Joydeep ,  VEMBU, Balaji ,  K, Pattabhiraman ,  PUFFER, David ,  COWPERTHWAITE, David J. ,  SANKARAN, Rajesh M. ,  SINGH, Satyeshwar ,  KP, Sameer ,  SHAH, Ankur N. ,  TIAN, Kun

IPC: G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：EP3401874A1

公开(公告)日：2018-11-14

申请号：EP18159601.6

申请日：2018-03-01

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  WALD, Ingo ,  PUFFER, David ,  MAIYURAN, Subramaniam M. ,  SURTI, Prasoonkumar ,  VEMBU, Balaji ,  LUEH, Guei-Yuan ,  RAMADOSS, Murali ,  APPU, Abhishek R. ,  RAY, Joydeep

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：EP3385847A1

公开(公告)日：2018-10-10

申请号：EP18160824.1

申请日：2018-03-08

Applicant: INTEL Corporation

Inventor： RAY, Joydeep ,  KOKER, Altug ,  VALERIO, James A. ,  PUFFER, David ,  APPU, Abhishek R. ,  JUNKINS, Stephen

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/621 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：EP4235441A1

公开(公告)日：2023-08-30

申请号：EP23151691.5

申请日：2023-01-16

Applicant: INTEL Corporation

Inventor： PAL, Rahul ,  BALLE, Susanne M. ,  PUFFER, David ,  CHITLUR, Nagabhushan

IPC: G06F12/0831 ,  G06F12/0888 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  G06F12/0813 ,  G06F12/02

Abstract: In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.