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21.
公开(公告)号:US20240031219A1
公开(公告)日:2024-01-25
申请号:US18478514
申请日:2023-09-29
Applicant: Intel Corporation
Inventor: John J. Browne , Kshitij Arun Doshi , Francesc Guim Bernat , Adrian Hoban , Mats Agerstam , Shekar Ramachandran , Thijs Metsch , Timothy Verrall , Ciara Loftus , Emma Collins , Krzysztof Kepka , Pawel Zak , Aibhne Breathnach , Ivens Zambrano , Shanshu Yang
IPC: H04L41/0654 , H04L41/0806
CPC classification number: H04L41/0654 , H04L41/0806
Abstract: Methods, apparatus, and systems are disclosed for mapping active assurance intents to resource orchestration and life cycle management. An example apparatus disclosed herein is to reserve a probe on a compute device in a cluster of compute devices based on a request to satisfy a resource availability criterion associated with a resource of the cluster, apply a risk mitigation operation based on the resource availability criterion before deployment of a workload to the cluster, and monitor whether the criterion is satisfied based on data from the probe after deployment of the workload to the cluster.
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公开(公告)号:US11880714B2
公开(公告)日:2024-01-23
申请号:US17521592
申请日:2021-11-08
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Ned Smith , Thomas Willhalm , Timothy Verrall
CPC classification number: G06F9/5027 , G06F1/26 , G06F1/3293 , G06F9/45558 , G06F9/48 , G06F9/485 , G06F9/4806 , G06F9/4843 , G06F9/4856 , G06F9/4881 , G06F9/4893 , G06F9/50 , G06F9/5005 , G06F9/505 , G06F9/5044 , G06F9/5055 , G06F9/5061 , G06F9/5072 , G06F9/5094 , G06F9/54 , G06F9/547 , G06F2009/45595
Abstract: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.
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公开(公告)号:US11611491B2
公开(公告)日:2023-03-21
申请号:US16235159
申请日:2018-12-28
Applicant: Intel Corporation
Inventor: Ned M. Smith , Ben McCahill , Francesc Guim Bernat , Felipe Pastor Beneyto , Karthik Kumar , Timothy Verrall
IPC: H04L41/5009 , H04L67/10 , H04L41/5019 , H04L67/51 , H04L67/12
Abstract: An architecture to enable verification, ranking, and identification of respective edge service properties and associated service level agreement (SLA) properties, such as in an edge cloud or other edge computing environment, is disclosed. In an example, management and use of service information for an edge service includes: providing SLA information for an edge service to an operational device, for accessing an edge service hosted in an edge computing environment, with the SLA information providing reputation information for computing functions of the edge service according to an identified SLA; receiving a service request for use of the computing functions of the edge service, under the identified SLA; requesting, from the edge service, performance of the computing functions of the edge service according to the service request; and tracking the performance of the computing functions of the edge service according to the service request and compliance with the identified SLA.
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公开(公告)号:US11537447B2
公开(公告)日:2022-12-27
申请号:US16969728
申请日:2018-06-29
Applicant: INTEL CORPORATION
Inventor: Francesc Guim Bernat , Karthik Kumar , Susanne M. Balle , Ignacio Astilleros Diez , Timothy Verrall , Ned M. Smith
Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
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25.
公开(公告)号:US11522682B2
公开(公告)日:2022-12-06
申请号:US17332733
申请日:2021-05-27
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Suraj Prabhakaran , Kshitij A. Doshi , Timothy Verrall
IPC: H04L9/08 , G06F3/06 , G06F9/50 , H04L69/12 , H04L69/32 , G06F16/25 , G06F16/2453 , H04L49/9005 , G11C8/12 , G11C29/02 , H04L41/0896 , G06F30/34 , B25J15/00 , G06F1/18 , G06F1/20 , G06F11/34 , G06F15/78 , H04L41/5025 , H04L67/1008 , H05K7/14 , H05K7/18 , H05K7/20 , H04L67/1001 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/22 , G06F16/2455 , G06F12/02 , G06F12/14 , G06F13/16 , G06F15/173 , G06F13/40 , G06F13/42 , G06F9/448 , G06F9/28 , G06F15/16 , H04L41/0893 , H04L69/22 , H04L69/321 , H04L41/0213 , H04L41/0668 , H04L41/0677 , H04L45/28 , H04L45/7453 , H04L47/11 , H04L47/125 , H04L49/00 , H04L49/351 , G06F9/4401 , G06F9/445 , G06F12/06 , G06F16/23 , G06F16/248 , G06F16/901 , G06F16/11 , G06F9/44 , G06F9/48 , G06F21/10 , G06N3/063 , G06Q10/06 , G06Q30/02 , H04L41/14 , H04L41/5019 , H04L49/40 , H04L9/40 , G06F12/0802 , G06F12/1045
Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.
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公开(公告)号:US11469953B2
公开(公告)日:2022-10-11
申请号:US15716890
申请日:2017-09-27
Applicant: Intel Corporation
Inventor: John J. Browne , Timothy Verrall , Maryam Tahhan , Michael J. McGrath , Sean Harte , Kevin Devey , Jonathan Kenny , Christopher MacNamara
IPC: H04L41/0873 , H04L41/0806 , H04L41/0823 , H04L41/08 , H04L41/0896 , H04L41/50
Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
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公开(公告)号:US11456966B2
公开(公告)日:2022-09-27
申请号:US17500543
申请日:2021-10-13
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Mark A. Schmisseur , Timothy Verrall
IPC: G06F15/173 , H04L47/765 , H04L47/70 , G06F9/50 , G06N20/00
Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (Al) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the Al circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.
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28.
公开(公告)号:US11444846B2
公开(公告)日:2022-09-13
申请号:US16368980
申请日:2019-03-29
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Kapil Sood , Tarun Viswanathan , Kshitij Doshi , Timothy Verrall , Ned M. Smith , Manish Dave , Alex Vul
IPC: H04L41/00 , H04L9/40 , H04L41/5003 , H04L41/0893 , G06F21/57
Abstract: Technologies for accelerated orchestration and attestation include multiple edge devices. An edge appliance device performs an attestation process with each of its components to generate component certificates. The edge appliance device generates an appliance certificate that is indicative of the component certificates and a current utilization of the edge appliance device and provides the appliance certificate to a relying party. The relying party may be an edge orchestrator device. The edge orchestrator device receives a workload scheduling request with a service level agreement requirement. The edge orchestrator device verifies the appliance certificate and determines whether the service level agreement requirement is satisfied based on the appliance certificate. If satisfied, the workload is scheduled to the edge appliance device. Attestation and generation of the appliance certificate by the edge appliance device may be performed by an accelerator of the edge appliance device. Other embodiments are described and claimed.
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公开(公告)号:US11416295B2
公开(公告)日:2022-08-16
申请号:US16563171
申请日:2019-09-06
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Suraj Prabhakaran , Timothy Verrall , Thomas Willhalm , Mark Schmisseur
IPC: G06F9/50 , G06F16/27 , G06F21/62 , G06F16/23 , H04L9/06 , H04L9/32 , H04L41/12 , H04L47/70 , H04L67/52 , H04L67/60 , G06F21/60 , H04L9/08
Abstract: Technologies for providing efficient data access in an edge infrastructure include a compute device comprising circuitry configured to identify pools of resources that are usable to access data at an edge location. The circuitry is also configured to receive a request to execute a function at an edge location. The request identifies a data access performance target for the function. The circuitry is also configured to map, based on a data access performance of each pool and the data access performance target of the function, the function to a set of the pools to satisfy the data access performance target.
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公开(公告)号:US20220222274A1
公开(公告)日:2022-07-14
申请号:US17580436
申请日:2022-01-20
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Suraj Prabhakaran , Ramanathan Sethuraman , Timothy Verrall , Ned Smith
Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
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