公开(公告)号：US12243875B2

公开(公告)日：2025-03-04

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US12183668B2

公开(公告)日：2024-12-31

申请号：US17213144

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Rajat Paul

IPC: H01L23/522 ,  H01L27/01 ,  H01L29/786 ,  H01L49/02 ,  H10B12/00

Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

公开(公告)号：US20240222521A1

公开(公告)日：2024-07-04

申请号：US18091676

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Evan A. Clinton ,  Rohit V. Galatage ,  Cheng-Ying Huang ,  Jack T. Kavalieros ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jami A. Wiedemer

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Technologies for ribbon field-effect transistors with variable nanoribbon numbers are disclosed. In an illustrative embodiment, a stack of semiconductor nanoribbons is formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be removed. In other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be removed.

公开(公告)号：US12020929B2

公开(公告)日：2024-06-25

申请号：US16454568

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L23/498 ,  H01L21/02 ,  H01L25/065

CPC classification number: H01L21/02532 ,  H01L21/02472 ,  H01L23/49827 ,  H01L25/0657

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.

公开(公告)号：US20240204103A1

公开(公告)日：2024-06-20

申请号：US18065657

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Cheng-Ying Huang ,  Dan S. Lavric ,  Sarah Atanasov ,  Shao Ming Koh ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Jami Wiedemer ,  Munzarin Qayyum ,  Evan Clinton

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/49 ,  H01L2029/7858

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include multiple dipole materials, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material and a gate dielectric material between the gate electrode material and the channel material, where the gate dielectric material includes a first dipole material and a second dipole material where one of the first and second dipole materials is a P-shifter dipole material and the other one is an N-shifter dipole material.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

公开(公告)号：US20230420460A1

公开(公告)日：2023-12-28

申请号：US17847628

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Quan Shi ,  Rohit Galatage ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Jami A. Wiedemer ,  Gilbert Dewey ,  Mauro J. Kobrinsky ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L27/0924 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L23/481

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

公开(公告)号：US20230402513A1

公开(公告)日：2023-12-14

申请号：US17838646

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Willy Rachmady ,  Subrina Rafique ,  Nitesh Kumar ,  Cheng-Ying Huang ,  Jami A. Wiedemer ,  Nicloe K. Thomas ,  Munzarin F. Qayyum ,  Patrick Morrow ,  Marko Radosavljevic ,  Mauro J. Kobrinsky

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.

公开(公告)号：US20230402507A1

公开(公告)日：2023-12-14

申请号：US17838637

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Willy Rachmady ,  Cheng-Ying Huang ,  Jami A. Wiedemer ,  Munzarin F. Qayyum ,  Nicole K. Thomas ,  Patrick Morrow ,  Marko Radosavljevic ,  Mauro J. Kobrinsky

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit structure includes a second device stacked vertically above a first device. The first device includes (i) a first source or drain region, (ii) a first source or drain contact coupled to the first source or drain region, and (iii) a first layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact. The second device includes (i) a second source or drain region, (ii) a second source or drain contact coupled to the second source or drain region, and (iii) a second layer comprising a second metal and second one or more semiconductor materials between at least a section of the second source or drain region and the second source or drain contact. In an example, the first metal and the second metal are different.

公开(公告)号：US20230395678A1

公开(公告)日：2023-12-07

申请号：US17831802

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Munzarin F. Qayyum ,  Nicole K. Thomas ,  Jami A. Wiedemer ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Nitesh Kumar ,  Kai Loon Cheong ,  Venkata Vasiraju

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L27/0924

Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.