公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/768

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20250087587A1

公开(公告)日：2025-03-13

申请号：US18465779

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Architectures and process flows for an embedded organic bridge component for semiconductor packages. The bulk of the substrate package fabrication can be done using conventional processing steps to meet core geometries (e.g., 9/12) with associated equipment and clean room protocols. Separately the organic bridge component is fabricated to embed into the substrate package at a location where the high-speed input/output (I/O) performance and high-density (HD) geometry are required. The organic bridge component is fabricated as required to meet the HD geometry (e.g., 3/3, or less). During assembly, the embedded organic bridge component can be attached into a cavity in the substrate package.

公开(公告)号：US20240222249A1

公开(公告)日：2024-07-04

申请号：US18148355

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Oladeji T. Fadayomi ,  Manuel Gadogbe ,  Matthew L. Tingey

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: In one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.

公开(公告)号：US20240222248A1

公开(公告)日：2024-07-04

申请号：US18147457

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Sashi Shekhar Kandanur ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/306

CPC classification number: H01L23/49827 ,  H01L21/30604 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/78

Abstract: Architectures and methods for metal lamination on a glass layer or glass core. The architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. The anchors hold the conductive pads and conductive material planes down to the glass surface. The architecture includes various combinations of end anchors and through glass via (TGV) anchors.

公开(公告)号：US20240213169A1

公开(公告)日：2024-06-27

申请号：US18086265

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L23/5386 ,  H01L23/645 ,  H10B80/00 ,  H01L24/32

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

公开(公告)号：US20240176084A1

公开(公告)日：2024-05-30

申请号：US18059923

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Brandon Christian Marin ,  Gang Duan ,  Bai Nie

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/136

Abstract: A PIC first patch architecture includes a solderless electrical connection at a die interconnect surface. Redistribution layers (RDLs) are patterned onto a face of an integrated circuit (IC) die and photonic integrated circuit (PIC) die prior to placement of the RDLs into a cavity in a glass layer. Optical interconnections for the PIC die are protected during RDL patterning and optical waveguides may be patterned into the glass layer fore or after assembling the PIC first patch including the RDL and glass layer.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US11670504B2

公开(公告)日：2023-06-06

申请号：US16419426

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Andrew J. Brown ,  Dilan Seneviratne

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/02345 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02194 ,  H01L21/76825 ,  H01L21/76841 ,  H01L23/5329 ,  H01L23/53228 ,  H01L28/60

Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.

公开(公告)号：US20220406618A1

公开(公告)日：2022-12-22

申请号：US17351537

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Leonel R. Arana ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Brandon Christian Marin

IPC: H01L21/48 ,  H01L23/538 ,  H01L21/768

Abstract: Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.