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21.
公开(公告)号:US20210349512A1
公开(公告)日:2021-11-11
申请号:US17443374
申请日:2021-07-26
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Alexander Bachmutsky , Dimitrios Ziakas , Rita D. Gupta
IPC: G06F1/26
Abstract: In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.
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公开(公告)号:US20210328886A1
公开(公告)日:2021-10-21
申请号:US17359349
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Kshitij Doshi , Marcos Carranza , Thijs Metsch , Adrian Hoban
Abstract: Example methods, apparatus, and systems to facilitate service proxying are disclosed. An example apparatus includes interface circuitry to access a service request intercepted by from an infrastructure processing unit, the service request corresponding to a first node; instructions in the apparatus; and infrastructure sidecar circuitry to execute the instructions to: identify an active service instance corresponding to the service request; compare first telemetry data corresponding to the active service instance to a service quality metric; select a second node to service the service request based on the comparison and further telemetry data; and cause transmission of the service request to the second node.
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公开(公告)号:US11138101B2
公开(公告)日:2021-10-05
申请号:US16204772
申请日:2018-11-29
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Brian J. Slechta
IPC: G06F12/00 , G06F12/02 , G06F12/0893
Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
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公开(公告)号:US11005968B2
公开(公告)日:2021-05-11
申请号:US15435371
申请日:2017-02-17
Applicant: Intel Corporation
Inventor: Karthik Kumar , Francesc Guim Bernat , Thomas Willhalm , Raj K. Ramanujan , Andrew J. Herdrich
IPC: H04L29/08 , H04L12/861 , H04L12/927 , H04L12/801
Abstract: There is disclosed in an example, a fabric interface device, having: a fabric interconnect to communicatively couple to a fabric; service level agreement (SLA) input logic to receive an SLA data structure from a controller, the SLA data structure providing an end-to-end SLA for a resource flow provided by a plurality of resources, and comprising QoS metrics for the resources; and SLA output logic to propagate the QoS metrics out to the resources via the fabric interconnect.
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25.
公开(公告)号:US10824358B2
公开(公告)日:2020-11-03
申请号:US15720653
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Susanne M. Balle , Murugasamy K. Nachimuthu , Daniel Rivas Barragan
IPC: G06F11/00 , G06F3/06 , G06F16/174 , G06F21/57 , G06F21/73 , G06F8/65 , H04L12/24 , H04L29/08 , G06F11/30 , G06F9/50 , H03M7/30 , H03M7/40 , H04L12/26 , H04L12/813 , H04L12/851 , G06F11/07 , G06F11/34 , G06F7/06 , G06T9/00 , H03M7/42 , H04L12/28 , H04L12/46 , H04L29/12 , G06F13/16 , G06F21/62 , G06F21/76 , H03K19/173 , H04L9/08 , H04L12/933 , G06F9/38 , G06F9/48 , G06F12/02 , G06F12/06 , G06T1/20 , G06T1/60 , G06F9/54 , G06F8/656 , G06F8/658 , G06F8/654 , G06F9/4401 , H01R13/453 , H01R13/631 , H05K7/14 , H04L12/911 , G06F11/14 , H04L29/06 , G06F15/80
Abstract: Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.
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26.
公开(公告)号:US20200228626A1
公开(公告)日:2020-07-16
申请号:US16829814
申请日:2020-03-25
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Slawomir Putyrski , Susanne M. Balle , Thomas Willhalm , Karthik Kumar
IPC: H04L29/08 , H04L12/911
Abstract: Technologies for providing advanced resource management in a disaggregated environment include a compute device. The compute device includes circuitry to obtain a workload to be executed by a set of resources in a disaggregated system, query a sled in the disaggregated system to identify an estimated time to complete execution of a portion of the workload to be accelerated using a kernel, and assign, in response to a determination that the estimated time to complete execution of the portion of the workload satisfies a target quality of service associated with the workload, the portion of the workload to the sled for acceleration.
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公开(公告)号:US20190281132A1
公开(公告)日:2019-09-12
申请号:US16415138
申请日:2019-05-17
Applicant: Intel Corporation
Inventor: Ramanathan Sethuraman , Timothy Verrall , Ned M. Smith , Thomas Willhalm , Brinda Ganesh , Francesc Guim Bernat , Karthik Kumar , Evan Custodio , Suraj Prabhakaran , Ignacio Astilleros Diez , Nilesh K. Jain , Ravi Iyer , Andrew J. Herdrich , Alexander Vul , Patrick G. Kutch , Kevin Bohan , Trevor Cooper
Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
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公开(公告)号:US10402124B2
公开(公告)日:2019-09-03
申请号:US15474044
申请日:2017-03-30
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Mark Schmisseur , Karthik Kumar , Thomas Willhalm , Lidia Warnes
Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.
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29.
公开(公告)号:US10387259B2
公开(公告)日:2019-08-20
申请号:US14751760
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Karthik Kumar , Martin Dimitrov , Thomas Willhalm
Abstract: An apparatus is described. The apparatus includes a memory controller having a programmable component. The programmable component is to implement a data checking function. The programmable component is to receive and process partial results of the data checking function from two or more DIMM cards that are coupled to the memory controller.
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公开(公告)号:US20190230191A1
公开(公告)日:2019-07-25
申请号:US16369384
申请日:2019-03-29
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Petar Torre , Ned Smith
IPC: H04L29/08 , H04L12/911 , H04L12/66
Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.
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