公开(公告)号：EP3195358A1

公开(公告)日：2017-07-26

申请号：EP14901871.5

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： LEE, Kevin J. ,  SARASWAT, Ruchir ,  ZILLMANN, Uwe ,  RAO, Valluri Bob ,  LUND-LARSEN, Tor ,  COWLEY, Nicholas P.

IPC: H01L27/04 ,  H01L21/60 ,  B81B7/02

CPC classification number: H04R1/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2207/096 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2203/0109 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27618 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83438 ,  H01L2224/8346 ,  H01L2224/83488 ,  H01L2224/8359 ,  H01L2224/83688 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166 ,  H04R1/406 ,  H04R19/005 ,  H04R19/04 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2221/68304

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了具有使用硅通孔（TSV）和相关技术和配置的集成麦克风装置的裸片。 在一个实施例中，一种设备包括装置，该装置包括具有第一侧和与第一侧相对设置的第二侧的半导体衬底，形成在半导体衬底的第一侧上的互连层，形成的硅通孔（TSV） 通过半导体衬底并且被配置为在半导体衬底的第一侧和半导体衬底的第二侧之间路由电信号，以及形成在半导体衬底的第二侧上并且与TSV电耦合的麦克风器件。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP3178162A1

公开(公告)日：2017-06-14

申请号：EP14899177.1

申请日：2014-08-07

Applicant: Intel Corporation

Inventor： GOLDMAN, Richard J. ,  LEE, Kevin J. ,  SARASWAT, Ruchir ,  ZILLMANN, Uwe ,  COWLEY, Nicholas P.

IPC: H03H7/00 ,  H04B1/00

CPC classification number: H01L24/09 ,  G06F1/16 ,  H01F27/2804 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2223/6616 ,  H01L2223/6661 ,  H01L2223/6677 ,  H01L2224/0233 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H03H7/42 ,  H03H9/64

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Abstract translation: 所描述的是，它包括一个设备，包括：第一对具有再分布层（RDL）的的背面侧; 和设置在背面侧的一个或多个无源平面器件，所述一个或多个无源平面器件形成在RDL。

公开(公告)号：EP3198637B1

公开(公告)日：2019-06-26

申请号：EP14902796.3

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： LEE, Kevin J.

IPC: H01L23/48

公开(公告)号：EP3298608A1

公开(公告)日：2018-03-28

申请号：EP15892750.9

申请日：2015-05-18

Applicant: Intel Corporation

Inventor： LEE, Kevin J. ,  WANG, Yih ,  TAN, Elliot N.

IPC: G11C5/02 ,  G11C5/06

CPC classification number: H01L45/1683 ,  G11C5/063 ,  G11C11/161 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08

Abstract: Described is an apparatus which comprises: non-orthogonal transistor fins which are non-orthogonal to transistor gates; diffusion contacts with non-right angled sides, the diffusion contacts coupled to the non-orthogonal transistor fins; first vias; and at least one memory element coupled to at least one of the diffusion contacts through at least one of the first vias.