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    Calibrated biasing of sleep transistor in integrated circuits
    22.
    发明授权
    Calibrated biasing of sleep transistor in integrated circuits 有权

    公开(公告)号：US10454476B2

    公开(公告)日：2019-10-22

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS
    24.
    发明申请
    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190044512A1

    公开(公告)日：2019-02-07

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  H03K19/0013

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    ASSIST CIRCUIT FOR MEMORY
    27.
    发明申请
    ASSIST CIRCUIT FOR MEMORY 审中-公开

    公开(公告)号：US20160225419A1

    公开(公告)日：2016-08-04

    申请号：US15094755

    申请日：2016-04-08

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC: G11C7/12 ,  G11C7/22

    CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    Assist circuit for memory
    28.
    发明授权
    Assist circuit for memory 有权
    辅助电路用于记忆

    公开(公告)号：US09355694B2

    公开(公告)日：2016-05-31

    申请号：US14229767

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C17/16

    CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    Abstract translation: 实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

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