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公开(公告)号：US09218046B2
公开(公告)日：2015-12-22
申请号：US14564436
申请日：2014-12-09
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US08775834B2
公开(公告)日：2014-07-08
申请号：US13791089
申请日：2013-03-08
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08738942B2
公开(公告)日：2014-05-27
申请号：US13721794
申请日：2012-12-20
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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24.发明授权公开(公告)号：US12166688B2
公开(公告)日：2024-12-10
申请号：US18039166
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Nilesh Jain , Rajesh Poornachandran , Eriko Nurvitadhi , Anahita Bhiwandiwalla , Juan Pablo Munoz , Ravishankar Iyer , Chaunte W. Lacewell
IPC: H04L47/726 , H04L47/2425 , H04L47/765
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to optimize resources in edge networks. An example apparatus includes agent managing circuitry to invoke an exploration agent to identify platform resource devices, select a first one of the identified platform resource devices, and generate first optimization metrics for the workload corresponding to the first one of the identified platform resource devices, the first optimization metrics corresponding to a first path. The example agent is to further select a second one of the identified platform resource devices, generate second optimization metrics for the workload corresponding to the second one of the identified platform resource devices, the second optimization metrics corresponding to a second path. The example apparatus also includes benchmark managing circuitry to embed second semantic information to the workload, the second semantic information including optimized graph information and platform structure information corresponding to the second one of the identified platform resource devices, and reconfiguration managing circuitry to select the first path or the second path during runtime based on (a) service level agreement (SLA) information and (b) utilization information corresponding to the first and second identified platform resource devices.
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25.发明授权公开(公告)号：US11989587B2
公开(公告)日：2024-05-21
申请号：US16914301
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Rameshkumar Illikkal , Andrew J. Herdrich , Francesc Guim Bernat , Ravishankar Iyer
CPC classification number: G06F9/5016 , G06F9/30101 , G06F9/4881 , G06F11/3037 , G06F11/3466
Abstract: An apparatus and method for dynamic resource allocation with mile/performance markers. For example, one embodiment of a processor comprises: resource allocation circuitry to allocate a plurality of hardware resources to a plurality of workloads including priority workloads associated with one or more guaranteed performance levels; and monitoring circuitry to evaluate execution progress of a workload across a plurality of nodes, each node to execute one or more processing stages of the workload, wherein the monitoring circuitry is to evaluate the execution progress of the workload, at least in part, by reading progress markers advertised by the workload at the specified processing stages, wherein the monitoring circuitry is to detect that the workload may not meet one of the guaranteed performance levels based on the progress markers, and wherein the resource allocation circuitry, responsive to the monitoring circuitry, is to reallocate one or more of the plurality of hardware resources to improve the performance level of the workload.
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Patent Agency Ranking
公开(公告)号：US10860853B2
公开(公告)日：2020-12-08
申请号：US15582106
申请日：2017-04-28
Applicant: Intel Corporation
Inventor： Carl S. Marshall , Ravishankar Iyer , Sejun Kim , Doye C. Emelue
Abstract: Methods, apparatus, and system to enable and implement interaction between a computer device and a person (or people) such as via images and objects identified in such images. The interaction may make possible rapid and convenient machine learning with respect to such objects.
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公开(公告)号：US10552550B2
公开(公告)日：2020-02-04
申请号：US14866897
申请日：2015-09-26
Applicant: Intel Corporation
Inventor： Glen J. Anderson , Kevin W. Bross , Shawn S. Mceuen , Mark R. Francis , Yevgeniy Y. Yarmosh , Blanka Vlasak , Gregory A. Peek , Therese E. Dugan , Cory A. Harris , Ravishankar Iyer , Omesh Tickoo , David I. Poisner
Abstract: Technologies for physical programming include a model compute system to determine one or more physical blocks assembled in a constructed model. The model compute system determines rules associated with the one or more physical blocks in which at least one rule defines a behavior of the constructed model and determines a program stack for execution by the model compute system based on the rules associated with the one or more physical blocks.
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公开(公告)号：US10074205B2
公开(公告)日：2018-09-11
申请号：US15252126
申请日：2016-08-30
Applicant: Intel Corporation
Inventor： Glen J. Anderson , David I. Poisner , Ravishankar Iyer , Mark Francis , Michael E. Kounavis , Omesh Tickoo
CPC classification number: G06T13/20 , A63F13/52 , A63F13/60 , G06T7/344 , G06T7/55 , G06T7/75 , G06T7/97 , G06T2207/10016 , G06T2213/08
Abstract: Methods, apparatus, and systems to create, output, and use animation programs comprising keyframes, objects, object states, and programming elements. Objects, object states, and programming elements may be created through image analysis of image input. Animation programs may be output as videos, as non-linear interactive experiences, and/or may be used to control electronic actuators in articulated armatures.
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29.发明授权公开(公告)号：US09760794B2
公开(公告)日：2017-09-12
申请号：US14866606
申请日：2015-09-25
Applicant: INTEL CORPORATION
Inventor： Teahyung Lee , Myung Hwangbo , Tanfer Alan , Omesh Tickoo , Ravishankar Iyer
CPC classification number: G06K9/4647 , G06K9/00986 , G06K9/42 , G06K9/4609 , G06K9/4642 , G06K9/4652 , G06K9/4661 , G06K9/481 , G06K9/6212 , G06K2009/485
Abstract: Techniques for a system, article, and method of low-complexity histogram of gradients generation for image processing may include histogram of gradients generation for image processing including the following operations: obtaining image data including horizontal and vertical gradient components of individual pixels of an image; associating the horizontal and vertical gradient components of the same pixel with one of a plurality of angular channels depending on the values of the horizontal and vertical gradient components; determining a gradient magnitude and a gradient orientation of individual angular channels after the horizontal and vertical gradient components are assigned to the channels; and generating a histogram of gradients by using the gradient direction and gradient magnitude of the angular channels.
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公开(公告)号：US20170192887A1
公开(公告)日：2017-07-06
申请号：US15401220
申请日：2017-01-09
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Edwin Verplanke , Ravishankar Iyer , Christopher C. Gianos , Jeffrey D. Chamberlain , Ronak Singhal , Julius Mandelblat , Bret L. Toll
IPC: G06F12/0804 , G06F12/084 , G06F12/0897 , G06F12/0864 , G06F12/0875 , G06F12/0811 , G06F12/0842
CPC classification number: G06F12/0804 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0848 , G06F12/0864 , G06F12/0875 , G06F12/0895 , G06F12/0897 , G06F12/123 , G06F12/128 , G06F2212/1004 , G06F2212/1016 , G06F2212/1024 , G06F2212/604
Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.
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