公开(公告)号：US11387224B2

公开(公告)日：2022-07-12

申请号：US16158186

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Zhimin Wan ,  Yikang Deng ,  Junnan Zhao ,  Chong Zhang ,  Chandra Mohan M Jha ,  Ying Wang ,  Kyu-oh Lee

IPC: H01L23/34 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  F28D20/02

Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.

公开(公告)号：US20200243418A1

公开(公告)日：2020-07-30

申请号：US16256831

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Zhimin Wan ,  Shankar Devasenathipathy ,  Je-Young Chang

IPC: H01L23/433 ,  H01L21/48 ,  F28F19/01

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

公开(公告)号：US20200211927A1

公开(公告)日：2020-07-02

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US12266589B2

公开(公告)日：2025-04-01

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US12094800B2

公开(公告)日：2024-09-17

申请号：US16721809

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Jin Yang ,  Chia-Pin Chiu ,  Peng Li ,  Deepak Goyal

IPC: H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L23/3121 ,  H01L23/3185 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/538 ,  H01L24/32 ,  H01L2224/32225

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

公开(公告)号：US11854935B2

公开(公告)日：2023-12-26

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11521914B2

公开(公告)日：2022-12-06

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US20210398966A1

公开(公告)日：2021-12-23

申请号：US17462794

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Pooya Tadayon ,  Weihua Tang ,  Chandra M. Jha ,  Zhimin Wan

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/42 ,  H01L23/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

公开(公告)号：US20200312738A1

公开(公告)日：2020-10-01

申请号：US16364540

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Cheng Xu ,  Zhimin Wan ,  Yikang Deng ,  Chong Zhang ,  Ying Wang

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/367

Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one heat dissipation device attached to the electronic substrate, wherein the at least one heat dissipation device comprises a phase change material within a containment chamber. The at least one integrated circuit device may be thermally connected to the at least one heat dissipation device with at least one heat transfer structure formed in or on the electronic substrate.

公开(公告)号：US20200273776A1

公开(公告)日：2020-08-27

申请号：US16287728

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Zhimin Wan ,  Ying Wang ,  Yikang Deng ,  Chong Zhang ,  Jiwei Sun ,  Zhenguo Jiang ,  Kyu-Oh Lee

IPC: H01L23/467 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H01L23/473 ,  H01L23/31 ,  H01L23/66

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.