公开(公告)号：US20090083976A1

公开(公告)日：2009-04-02

申请号：US12010197

申请日：2008-01-22

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H05K3/00

CPC classification number: H05K3/423 ,  H05K1/116 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  Y10S205/92 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在第一载体上形成至少一个层间连接器，在第一载体上堆叠至少一个绝缘层，使得层间连接器暴露，去除第一载体，至少形成 绝缘层上的一个电路图案使得电路图案与层间连接器电耦合，可以用于增加电路图案的密度，因为该方法可以在不使用焊盘的情况下提供电路图案和通孔之间的电连接。

公开(公告)号：US20090027864A1

公开(公告)日：2009-01-29

申请号：US12007687

申请日：2008-01-14

Applicant: Chung-Woo Cho ,  Jong-Jin Lee ,  Soon-Jin Cho ,  Yong-Duk Lee ,  Ki-Young Yoo ,  Woo-Young Lee ,  Chin-Kwan Kim ,  Jong-Yong Kim ,  Dong-Ju Jeon

Inventor： Chung-Woo Cho ,  Jong-Jin Lee ,  Soon-Jin Cho ,  Yong-Duk Lee ,  Ki-Young Yoo ,  Woo-Young Lee ,  Chin-Kwan Kim ,  Jong-Yong Kim ,  Dong-Ju Jeon

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/3452 ,  H05K3/0032 ,  H05K2201/09845 ,  H05K2203/0594 ,  Y10T29/49165

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. A printed circuit board, which includes an insulation layer, a circuit pattern formed on a surface of the insulation layer that includes at least one pad, and a solder resist which covers the circuit pattern, and in which an opening is formed that exposes a portion of a side and a surface of the pad, can ensure a sufficient amount of attachment area for the pads and the solder resist, to strengthen the adhesion of the pads. Also, the adhesion can be increased between the electronic components and the printed circuit board, and heat release characteristics can be improved.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 一种印刷电路板，其包括绝缘层，形成在绝缘层的包括至少一个焊盘的表面上的电路图案和覆盖电路图案的阻焊剂，并且其中形成有露出部分的开口 的焊盘的侧面和表面，可以确保焊盘和阻焊剂的足够的附着面积，以增强焊盘的附着力。 此外，可以在电子部件和印刷电路板之间增加粘附性，并且可以提高散热特性。

公开(公告)号：US20080182354A1

公开(公告)日：2008-07-31

申请号：US11950249

申请日：2007-12-04

Applicant: Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

Inventor： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

IPC: H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14681 ,  H01L27/14689

Abstract: CMOS image sensors and related methods of fabricating CMOS image sensors are disclosed. Fabrication of a CMOS image sensor can include forming a first impurity region having a first conductivity type in a semiconductor substrate. A second impurity region having a second conductivity type is formed in the semiconductor substrate adjacent to the first impurity region. A third impurity region having the first conductivity type is formed in the semiconductor substrate and located below the second impurity region. A transfer gate is formed on the semiconductor substrate and at least partially overlaps the first, second, and third impurity regions. A photo sensitive device is formed in the semiconductor substrate and adjacent to one side of the transfer gate. A floating diffusion region is formed in the semiconductor substrate and located adjacent to an opposite side of the transfer gate from the photosensitive device.

Abstract translation: 公开了CMOS图像传感器和制造CMOS图像传感器的相关方法。 CMOS图像传感器的制造可以包括在半导体衬底中形成具有第一导电类型的第一杂质区域。 在与第一杂质区相邻的半导体衬底中形成具有第二导电类型的第二杂质区。 具有第一导电类型的第三杂质区形成在半导体衬底中并位于第二杂质区的下方。 传输栅极形成在半导体衬底上并且至少部分地与第一，第二和第三杂质区重叠。 光敏元件形成在半导体衬底中并与传输门的一侧相邻。 浮动扩散区域形成在半导体衬底中并且位于与传感栅极的与光敏器件相反的一侧。

公开(公告)号：US20070298546A1

公开(公告)日：2007-12-27

申请号：US11785093

申请日：2007-04-13

Applicant: Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

Inventor： Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

IPC: H01L21/00 ,  H01L21/44

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/42 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/1581 ,  H01L2224/05599

Abstract: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with the first circuit pattern is formed on the other surface, and a dielectric layer is selectively coated on the one surface such that the bump pad is exposed. The method includes layering a conductive layer on the other surface of the core board, coating a plating resist on the conductive layer, forming the bump by supplying electricity to the conductive layer to electroplate the bump pad, and removing the plating resist and the conductive layer. This makes it possible to omit the coining process and increase the density of the circuit by forming a fine bump by an electro tin plating method with small plating thickness deviation without designing additional plating bus lines, and improves the electrical performance without remaining plating bus lines.

Abstract translation: 公开了封装基板的制造方法。 制造封装衬底的方法是通过在芯板上的凸块焊盘上形成凸块，其中在一个表面上形成包括凸点焊盘的第一电路图案，与第一电路图形电连接的第二电路图案形成在 另一表面和电介质层被选择性地涂覆在一个表面上，使得凸块焊盘露出。 该方法包括在芯板的另一个表面上层叠导电层，在导电层上涂覆电镀抗蚀剂，通过向导电层供电以形成凸块以电镀凸块焊盘，以及去除电镀抗蚀剂和导电层 。 这样可以省略压印过程，并且通过在不设计附加的电镀母线的情况下通过电镀镀层方法形成微小的凸起来提高电路的密度，并且不需要剩余的电镀母线即可提高电气性能。

公开(公告)号：US07256495B2

公开(公告)日：2007-08-14

申请号：US10609499

申请日：2003-07-01

Applicant: Jong-Jin Lee ,  Young-Hwan Shin

Inventor： Jong-Jin Lee ,  Young-Hwan Shin

IPC: H01L23/48

CPC classification number: H01L21/4846 ,  H01L21/4857 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/243 ,  H05K3/426 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate is manufactured by electrolytically plating Au in a semi-additive manner without using any plating lead line. Such a package substrate includes a base substrate with a plurality of through holes, a first copper plated layer on portions of the base substrate and inner surfaces of the through holes, a plated pattern layer on the first copper plated layer, wire bonding pads on the plated pattern layer at an upper surface of the base substrate, the wire bonding pads including Au and not connected to a remnant of a plating lead line, solder ball pads on the plated pattern layer at a lower surface of the base substrate, the solder ball pads including Au and not connected to a remnant of a plating lead line, and a solder resist covering the base substrate and the plated pattern layer.

Abstract translation: 通过以半添加方式电镀Au而不使用任何电镀引线来制造封装基板。 这种封装基板包括具有多个通孔的基底基板，基底部分的部分上的第一镀铜层和通孔的内表面，第一镀铜层上的镀覆图案层， 在基底基板的上表面具有电镀图案层，引线接合焊盘包括Au并且未连接到电镀引线的残留物，在基底板的下表面处的镀覆图案层上的焊球焊盘，焊球 包括Au并且不连接到电镀引线的残余物的焊盘，以及覆盖基底衬底和镀覆图案层的阻焊剂。

公开(公告)号：US20160141246A1

公开(公告)日：2016-05-19

申请号：US14924217

申请日：2015-10-27

Applicant: Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

Inventor： Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

IPC: H01L23/522

CPC classification number: H01L23/485 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76882 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：第一层间绝缘层，包括第一沟槽，在衬底上，沿着侧壁形成的第一衬里层和第一沟槽的底表面，并且包括贵金属，贵金属属于第五周期之一， 是国际纯粹和应用化学联合会（IUPAC）编号之后的第六周期，属于周期图的第八至第十组之一，以及填充第一衬里层上的第一沟槽的第一金属线， 所述第一金属线的顶表面朝向所述第一沟槽的底表面具有凸形形状。

公开(公告)号：US08024856B2

公开(公告)日：2011-09-27

申请号：US12010197

申请日：2008-01-22

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/423 ,  H05K1/116 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  Y10S205/92 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在第一载体上形成至少一个层间连接器，在第一载体上堆叠至少一个绝缘层，使得层间连接器暴露，去除第一载体，至少形成 绝缘层上的一个电路图案使得电路图案与层间连接器电耦合，可以用于增加电路图案的密度，因为该方法可以在不使用焊盘的情况下提供电路图案和通孔之间的电连接。

公开(公告)号：US20100090351A1

公开(公告)日：2010-04-15

申请号：US12357643

申请日：2009-01-22

Applicant: Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

Inventor： Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L24/13 ,  H01L24/14 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: An electro component package is disclosed. The electro component package in accordance with an embodiment of the present invention includes a first package substrate having a first chip mounted on an upper surface thereof, the first chip having a through-via formed therein; a second package substrate being separated from the first package substrate and having a second chip mounted on an upper surface thereof; and a connection substrate having one end connected with an upper surface of the first chip and the other end connected with an upper surface of the second chip, the connection substrate electrically connecting the first chip with the second chip.

Abstract translation: 公开了电子部件封装。 根据本发明的实施例的电子部件封装包括：第一封装基板，其具有安装在其上表面上的第一芯片，所述第一芯片具有形成在其中的通孔; 第二封装衬底与第一封装衬底分离并且具有安装在其上表面上的第二芯片; 以及连接基板，其一端与所述第一芯片的上表面连接，所述另一端与所述第二芯片的上表面连接，所述连接基板将所述第一芯片与所述第二芯片电连接。

公开(公告)号：US20100056864A1

公开(公告)日：2010-03-04

申请号：US12515953

申请日：2007-11-21

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: A61B1/045 ,  H04N7/18

CPC classification number: A61B1/041 ,  A61B1/00158

Abstract: Provided are a capsule-type image photographing apparatus and endoscopy using the same. The apparatus includes a shell unit having a globular shape and a main body unit capable of freely rotating in the shell unit. The main body unit includes an image photographing system, a wireless transmitter, a battery, a counterweight for determining the center of gravity of the main body unit, and an encapsulant for fixing the image photographing system, the wireless transmitter, the battery, and the counterweight. The apparatus may be a long-distance capsule-type image photographing apparatus or a short-distance capsule-type image photographing apparatus depending on the position of the counterweight. By use of the long- and short-distance capsule-type image photographing apparatuses, the interior of the tested person's body can be effectively photographed.

Abstract translation: 提供了胶囊型图像拍摄装置和使用其的内窥镜检查。 该装置包括具有球形形状的壳单元和能够在壳单元中自由旋转的主体单元。 主体单元包括图像拍摄系统，无线发射器，电池，用于确定主体单元的重心的配重，以及用于固定图像拍摄系统，无线发射器，电池和 配重。 该装置可以是根据配重的位置的长距离胶囊型图像拍摄装置或短距离胶囊型图像拍摄装置。 通过使用长距离和短距离胶囊型图像拍摄装置，可以有效地拍摄被测试人体的内部。

公开(公告)号：US20080023624A1

公开(公告)日：2008-01-31

申请号：US11797561

申请日：2007-05-04

Applicant: Kyoung-Sik Moon ,  Bum-Suk Kim ,  Jong-Jin Lee ,  Yun-Ho Jang

Inventor： Kyoung-Sik Moon ,  Bum-Suk Kim ,  Jong-Jin Lee ,  Yun-Ho Jang

IPC: H01J40/14 ,  H01L31/18

CPC classification number: G02B3/08 ,  G02B3/0056 ,  G02B13/22 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02165

Abstract: An image sensor may include a plurality of photodiodes for performing a photo-electric conversion and a plurality of microlenses. Each of the microlenses is formed over one of the photodiodes. The image sensor may further include a vertical light generating portion formed over the microlenses and configured to refract each of plurality of incident light rays such that the light rays are vertically incident on the microlenses.

Abstract translation: 图像传感器可以包括用于执行光电转换和多个微透镜的多个光电二极管。 每个微透镜形成在一个光电二极管上。 图像传感器还可以包括形成在微透镜上的垂直光产生部分，并被配置为折射多个入射光线中的每一个，使得光线垂直入射在微透镜上。