公开(公告)号：AU2019274735A1

公开(公告)日：2020-12-10

申请号：AU2019274735

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.

公开(公告)号：CA3238600A1

公开(公告)日：2019-11-28

申请号：CA3238600

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

Abstract: An encoder partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.

公开(公告)号：CA3072997A1

公开(公告)日：2019-02-28

申请号：CA3072997

申请日：2018-08-10

Applicant: PANASONIC IP CORP AMERICA

Inventor： ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA ,  KANOH RYUICHI ,  LIM CHONG SOON ,  LIAO RU LING ,  SUN HAI WEI ,  SHASHIDHAR SUGHOSH PAVAN ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/117 ,  H04N19/157 ,  H04N19/80

Abstract: An image encoder is provided, which includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a non-rectangular shape (e.g., a triangular shape) and a second partition that are split from an image block. The boundary smoothing operation includes: first-predicting first values of a set of pixels of the first partition along the boundary, using information of the first partition; second-predicting second values of the set of pixels of the first partition along the boundary, using information of the second partition; weighting the first values and the second values; and encoding the first partition using the weighted first values and the weighted second values.

公开(公告)号：AU2010202485A1

公开(公告)日：2010-08-05

申请号：AU2010202485

申请日：2010-01-19

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  NISHI TAKAHIRO ,  SHIBAHARA YOUJI

IPC: H04M1/00 ,  H04N13/00 ,  H04N19/00 ,  H04N19/102 ,  H04N19/136 ,  H04N19/146 ,  H04N19/169 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/50 ,  H04N19/503 ,  H04N19/593 ,  H04N19/597 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/91

Abstract: A coding method includes: defining an access unit (S502 to S508); and coding each of the pictures included in the access unit, for each access unit (S526). The defining (S502 to S508) includes: determining a unit of coding for determining whether the pictures included in the access unit are to be uniformly coded on a per-field basis or on a per-frame basis (S502); and determining a field type for determining whether the pictures are to be uniformly coded as top fields or bottom fields (S504 to S508) when it is determined that the pictures included in the access unit are to be coded on a per-field basis. In the coding (S526), each of the pictures is coded for each access unit in a format determined in the determining of a unit of coding (S526) and in the determining of a field type (S502 to S508).

公开(公告)号：MX392880B

公开(公告)日：2025-03-24

申请号：MX2020009109

申请日：2020-09-02

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA ,  ABE KIYOFUMI ,  LIAO RU LING ,  KANOH RYUICHI ,  SHASHIDHAR SUGHOSH PAVAN ,  TOMA TADAMASA ,  NISHI TAKAHIRO

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/63

Abstract: Un codificador (100) que codifica un bloque actual en una imagen incluye circuitería y memoria. Usando la memoria, la circuitería: divide el bloque actual en un primer sub-bloque, un segundo sub-bloque y un tercer sub-bloque en una primera dirección, el segundo sub-bloque se ubica entre el primer sub-bloque y el tercer sub-bloque; impide dividir el segundo sub-bloque en dos particiones en la primera dirección; y codifica el primer sub-bloque, el segundo sub-bloque y el tercer sub-bloque.

公开(公告)号：MX2025000829A

公开(公告)日：2025-03-07

申请号：MX2025000829

申请日：2022-02-23

Applicant: PANASONIC IP CORP AMERICA

Inventor： LI JING YA ,  LIM CHONG SOON ,  TEO HAN BOON ,  KUO CHE-WEI ,  SUN HAI WEI ,  WANG CHU TONG ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA ,  KATO YUSUKE

IPC: H04N19/52 ,  H04N19/593

Abstract: Un codificador (100) incluye circuitos y una memoria acoplada a los circuitos. Los circuitos, en funcionamiento: determinan si un tamaño de un bloque actual, que es una unidad para la que se genera una lista de candidatos a vector que incluye candidatos a vector, es menor o igual que un umbral (S3001); cuando el tamaño del bloque actual es menor o igual que el umbral (SÍ en S3001), generan la lista de candidatos a vector registrando un candidato a vector de movimiento basado en la historia (HMVP) en la lista de candidatos a vector desde una tabla HMVP sin realizar un primer proceso de poda (S3002); cuando el tamaño del bloque actual es mayor que el umbral (NO en S3001), generan la lista de candidatos a vectores realizando el primer proceso de poda y registrando el candidato a vector HMVP en la lista de candidatos a vector desde la tabla HMVP (S3003); y codifican el bloque actual usando la lista de candidatos a vector (S3004).

公开(公告)号：IL318195A

公开(公告)日：2025-03-01

申请号：IL31819525

申请日：2025-01-06

Applicant: PANASONIC IP CORP AMERICA ,  GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

Inventor： GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

Abstract: An image decoder includes circuitry and a memory connected to the circuitry. In operation, the circuitry decodes a first bitstream to acquire a first image, decodes a second bitstream to acquire specification information specifying a particular region in the first image and a second image containing image data for the particular region, and generates a third image based on the first image, the specification information, and the second image.

公开(公告)号：AU2023201336A1

公开(公告)日：2023-04-06

申请号：AU2023201336

申请日：2023-03-03

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: An encoder (100) partitions into blocks using a set of block partition 5 modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks 10 obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block 15 partition mode indicating that the number of partitions is three. 19482302_1 (GHMatters) P114923.AU.1

公开(公告)号：AU2019274735B2

公开(公告)日：2022-12-15

申请号：AU2019274735

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.

公开(公告)号：MX2020012178A

公开(公告)日：2022-05-03

申请号：MX2020012178

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  SUN HAI WEI ,  TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  TEO HAN BOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LI JING YA ,  LIAO RU LING

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: Un codificador (100) parte en bloques mediante el uso de un conjunto de modos de partición de bloque obtenidos al combinar uno o más modos de partición de bloque que definen un tipo de partición. El conjunto de modos de partición de bloque incluye un primer modo de partición que define la dirección de partición y el número de particiones para partir un primer bloque, y un segundo modo de partición de bloque que define la dirección de partición y el número de particiones para partir un segundo bloque el cual es uno de los bloques obtenidos después de que se parte el primer bloque. Cuando el número de particiones del primer modo de partición de bloque es tres, el segundo bloque es un bloque central entre los bloques obtenidos después de partir el primer bloque, y la dirección de partición del segundo modo de partición de bloque es la misma que la dirección de partición del primer modo de partición de bloque, el segundo modo de partición de bloque incluye solo un modo de partición de bloque que indica que el número de particiones es tres.