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21.
公开(公告)号:EA021750B1
公开(公告)日:2015-08-31
申请号:EA201270461
申请日:2010-10-29
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , LI MIN , SUN HAI WEI , SHIBAHARA YOUJI , NISHI TAKAHIRO
IPC: H04N19/10
Abstract: Способдекодированиявключаетв себяполучениемножестванаборовпараметровквантованияиззаголовкакодированногопотока (S400); синтаксическийанализидентификатораиззаголовкакодированногоизображения, включенногов кодированныйпоток (S402); выборпоменьшеймереодногонаборапараметровквантованияизмножестванаборовпараметровквантованиянаосновесинтаксическипроанализированногоидентификатора (S404); определениетого, имеетлифлаг, синтаксическипроанализированныйиззаголовкакодированногоизображения, предварительноопределенноезначение (S408); формированиеновойматрицыквантованияиздругойматрицыквантования, когдафлагимеетпредварительноопределенноезначение (S410); декодированиекодированногоизображенияпутемобратногоквантованиякодированногоизображенияс использованиемсформированнойновойматрицыквантования (S412) идекодированиекодированногоизображенияпутемобратногоквантованиякодированногоизображенияс использованиемматрицыквантования, включеннойв выбранныйнаборпараметровквантования, когдафлагнеимеетпредварительноопределенноезначение (S414).
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公开(公告)号:MX2025000825A
公开(公告)日:2025-03-07
申请号:MX2025000825
申请日:2021-08-06
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , TEO HAN BOON , LI JING YA , KUO CHE-WEI , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO , KATO YUSUKE
IPC: H04N19/52 , H04N19/105 , H04N19/119 , H04N19/159 , H04N19/176
Abstract: Se proporciona un codificador (100) que incluye: circuitería; y una memoria acoplada a la circuitería, en el cual en operación, la circuitería: genera una imagen de predicción de un bloque actual a ser procesado, por medio del uso de un primer vector de movimiento (paso S3001); y actualiza una tabla de predictores de vectores de movimiento basados en la historia (HMVP) por medio del uso de un primer candidato que tiene el primer vector de movimiento, la tabla de HMVP almacena, en un método de primera entrada-primera salida (FIFO), una pluralidad de segundos candidatos cada uno que tiene un segundo vector de movimiento usado para un bloque procesado (paso S3002), y en la actualización de la tabla de HMVP, la circuitería: determina si un tamaño del bloque actual es menor que o igual a un tamaño umbral (paso S30021); y omite la actualización de la tabla de HMVP (paso S30022) cuando se determina que el tamaño del bloque actual es menor que o igual al tamaño umbral (Si en el paso S30021).
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公开(公告)号:MX2024004990A
公开(公告)日:2024-05-07
申请号:MX2024004990
申请日:2020-02-18
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LIAO RU LING , LI JING YA
IPC: H04N19/537 , H04N19/105 , H04N19/157 , H04N19/96
Abstract: Se proporciona un codificador de imagen el cual incluye conjunto de circuitos y una memoria acoplada al conjunto de circuitos. En operación, el conjunto de circuitos realiza: división de un bloque de imagen en una pluralidad de divisiones que incluyen una primera división que tiene una forma no rectangular (por ejemplo, una forma triangular) y una segunda división; predecir un primer vector de movimiento para la primera división y un segundo vector de movimiento para la segunda división; y codificar la primera división usando el primer vector de movimiento y la segunda división usando el segundo vector de movimiento.
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公开(公告)号:ZA202203500B
公开(公告)日:2023-08-30
申请号:ZA202203500
申请日:2022-03-25
Applicant: PANASONIC IP CORP AMERICA
Inventor: SUN HAI WEI , TEO HAN BOON , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO , LI JING YA , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING
Abstract: A coding device (100) is provided with a circuit (160) and a memory (162) connected to the circuit (160). The circuit (160): selects, from a plurality of tables which are used, during an operation, to correct a reference motion vector into a predetermined direction using a correction value designated by an index, and which have correction values with respectively different intervals between indexes, a first table used for a partition to be coded of an image in a moving image; writes a parameter indicating a first index to be selected from among indexes included in the first table; and codes the partition using the reference motion vector corrected by means of a correction value designated by the first index.
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25.
公开(公告)号:AU2023201643A1
公开(公告)日:2023-04-20
申请号:AU2023201643
申请日:2023-03-15
Applicant: PANASONIC IP CORP AMERICA
Inventor: LI JING YA , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO
IPC: H04N19/52
Abstract: An encoder (100) includes circuitry (160) and memory (162) connected to the circuitry (160). In operation, the circuitry (160): selects a first table to be 5 used for a current partition to be encoded in an image of a video, from among tables that are used to correct a base motion vector in a predetermined direction using a correction value specified by an index, the tables including correction values having varying differences between indexes; writes a parameter indicating a first index to be selected from among indexes included in the first 10 table; and encodes the current partition using the base motion vector corrected using a correction value specified by the first index. 19479675_1
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公开(公告)号:CA3100839C
公开(公告)日:2022-06-21
申请号:CA3100839
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/70
Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.
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公开(公告)号:MX2021000357A
公开(公告)日:2021-03-25
申请号:MX2021000357
申请日:2019-07-05
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LI JING YA , LIAO RU LING
IPC: H04N19/52
Abstract: Un codificador (100) incluye circuitería (160) y memoria (162) conectada a la circuitería (160). En operación, la circuitería (160): selecciona una primera tabla que se va a usar para una división actual que se va a codificar en una imagen de un video, de entre tablas que se usan para corregir un vector de movimiento base en una dirección predeterminada que usa un valor de corrección especificado por un índice, las tablas que incluyen valores de corrección que tienen diferencias variables entre índices; escribe un parámetro que indica un primer índice que se va a seleccionar de entre índices incluidos en la primera tabla; y codifica la división actual que usa el vector de movimiento base corregido al usar un valor de corrección especificado por el primer índice.
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28.
公开(公告)号:AU2019274735A1
公开(公告)日:2020-12-10
申请号:AU2019274735
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/70
Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.
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公开(公告)号:CA3238600A1
公开(公告)日:2019-11-28
申请号:CA3238600
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
Abstract: An encoder partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.
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公开(公告)号:CA3072997A1
公开(公告)日:2019-02-28
申请号:CA3072997
申请日:2018-08-10
Applicant: PANASONIC IP CORP AMERICA
Inventor: ABE KIYOFUMI , NISHI TAKAHIRO , TOMA TADAMASA , KANOH RYUICHI , LIM CHONG SOON , LIAO RU LING , SUN HAI WEI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LI JING YA
IPC: H04N19/117 , H04N19/157 , H04N19/80
Abstract: An image encoder is provided, which includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a non-rectangular shape (e.g., a triangular shape) and a second partition that are split from an image block. The boundary smoothing operation includes: first-predicting first values of a set of pixels of the first partition along the boundary, using information of the first partition; second-predicting second values of the set of pixels of the first partition along the boundary, using information of the second partition; weighting the first values and the second values; and encoding the first partition using the weighted first values and the weighted second values.
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