公开(公告)号：WO0227939A3

公开(公告)日：2002-05-30

申请号：PCT/US0128496

申请日：2001-09-14

Applicant: QUALCOMM INC

Inventor： HURT JAMES Y ,  LEVIN JEFFREY A ,  SCHLEGEL NIKOLAI

IPC: H03M13/09 ,  H03M13/15 ,  H03M13/47 ,  H04L1/00

CPC classification number: H04L1/0057 ,  H03M13/096 ,  H03M13/15 ,  H03M13/47 ,  H04L1/0041

Abstract: A method and apparatus for efficient encoding of linear block codes uses a lookup table including a set of impulse responses to support faster performance by encoding in parallel. Advantages include a scalability that is lacking in existing schemes.

Abstract translation: 用于高效编码线性分组码的方法和设备使用查找表，该查找表包括一组脉冲响应以通过并行编码来支持更快的性能。 优点包括现有方案缺乏的可扩展性。

公开(公告)号：WO0227959A3

公开(公告)日：2002-08-29

申请号：PCT/US0130417

申请日：2001-09-27

Applicant: QUALCOMM INC

Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

IPC: H03M13/27 ,  H04J11/00 ,  H04J13/00 ,  H04B1/707

CPC classification number: H04J13/0048 ,  H03M13/2703

Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299,600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

Abstract translation: 提供了一种用于通信系统中的信号的有效处理的方法和设备。 用于传输的信号的处理可以包括以编码速率1 / R编码数据块。 编码为数据块中的每个数据位产生R个数据符号。 RAM块（299,600）被划分为多个RAM块，以允许从多个RAM块同时读取数据符号以同时产生同相和四相数据符号。 至少两个扰码器（306和307）被用于同时加扰同相和四相数据符号。 沃尔什覆盖/求和块（700）跟随在扰码器之后，为来自通信系统的组合传输的信号提供有效的沃尔什覆盖和求和。

公开(公告)号：WO2004021589A9

公开(公告)日：2004-05-06

申请号：PCT/US0327016

申请日：2003-08-28

Applicant: QUALCOMM INC

Inventor： SCHLEGEL NIKOLAI ,  HOLENSTEIN CHRISTIAN ,  FILIPOVIC DANIEL ,  KASTURI NITIN

IPC: H03D3/00 ,  H04B1/30 ,  H04L25/06

CPC classification number: H04L25/063 ,  H03D3/008 ,  H04B1/30

Abstract: An apparatus for coarse compensation of a direct current (DC) offset in a direct to baseband receiver architecture utilizes a serial analog to digital converter (ADC), such as a Delta-Sigma converter, to convert the received signal to digital form. The output of the ADC is sampled for a predetermined number of samples and a counter coupled to the ADC is incremented each time the sample generated by the ADC is a logic one. The counter is not incremented if the sample from the ADC is a logic zero. After the predetermined number of samples is obtained, the counter value is indicative of the DC offset in the received signal. The counter value may be converted by a code converter to a correction value for easy operation of a digital to analog converter (DAC). If the number of samples from the ADC is a power of two, the code converted may be readily implemented by simply inverting the most significant bit (MSB) from the counter to thereby generate a twos complement version of the counter value. The correction value is coupled to the DAC to generate a compensation signal, which is provided to the received signal path in the form of a feedback signal to compensate for the DC offset.

Abstract translation: 用于直接到基带接收机架构中的直流（DC）偏移的粗略补偿的装置利用诸如Δ-Σ转换器的串行模数转换器（ADC）将接收的信号转换成数字形式。 对于预定数量的采样，ADC的输出被采样，并且每当由ADC产生的采样为逻辑1时，耦合到ADC的计数器递增。 如果来自ADC的采样为逻辑0，则计数器不递增。 在获得预定数量的样本之后，计数器值表示接收信号中的直流偏移。 计数器值可以由代码转换器转换成用于容易操作数模转换器（DAC）的校正值。 如果来自ADC的采样数是2的幂，则通过简单地将来自计数器的最高有效位（MSB）反相，从而生成计数器值的二进制补码版本，可以容易地实现转换代码。 校正值耦合到DAC以产生补偿信号，其以反馈信号的形式提供给接收信号路径以补偿DC偏移。

公开(公告)号：WO0229980A3

公开(公告)日：2003-01-16

申请号：PCT/US0128497

申请日：2001-09-14

Applicant: QUALCOMM INC

Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

IPC: H03M13/27 ,  H04B1/69 ,  H04L1/00 ,  H04M13/27

CPC classification number: H04L1/0071 ,  H03M13/2703 ,  H04L1/0041

Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

Abstract translation: 提供一种用于在通信系统中有效处理信号的方法和装置。 用于发送的信号的处理可以包括以编码率1 / R编码数据块。 编码为数据块中的每个数据位产生R个数据符号。 一块RAM（299,600）被划分成多个RAM块，以允许同时从多个RAM块读取数据符号以同时产生同相和四相数据符号。 至少两个加扰器（306和307）用于同时加扰同相和四相数据符号。 沃尔什覆盖/求和块（700）紧随其后的加扰器提供了有效的沃尔什覆盖和信号来自通信系统的组合传输信号。

公开(公告)号：WO0229979A2

公开(公告)日：2002-04-11

申请号：PCT/US0128492

申请日：2001-09-14

Applicant: QUALCOMM INC

Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

IPC: H03M13/27 ,  H04B1/707 ,  H04L1/00 ,  H04B

CPC classification number: H04L1/0071 ,  H03M13/2703 ,  H04B1/707 ,  H04L1/0043

Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299,600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quand-phase data symbols simultaneously. At least two scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block 700 provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

Abstract translation: 提供一种用于在通信系统中有效处理信号的方法和装置。 用于发送的信号的处理可以包括以编码率1 / R编码数据块。 编码为数据块中的每个数据位产生R个数据符号。 一块RAM（299,600）被划分成多个RAM块，以允许同时从多个RAM块读取数据符号，同时产生同相数据符号和相位数据符号。 至少两个对同相和四相数据符号进行加扰。 沃尔什覆盖/求和块700提供了用于来自通信系统的组合传输的信号的有效的沃尔什覆盖和求和。