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    Digital voltage amplifier with logarithmic and exponential conversion
    2.
    发明专利
    Digital voltage amplifier with logarithmic and exponential conversion 审中-公开
    具有逻辑和指数转换的数字电压放大器

    公开(公告)号：JP2009284498A

    公开(公告)日：2009-12-03

    申请号：JP2009157265

    申请日：2009-07-01

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： CHALLA RAGHU ,  KASTURI NITIN ,  SCHLEGEL NIKOLAI

    IPC: G06F1/00 ,  H03G3/20 ,  G06F1/03 ,  G06F7/52 ,  G06F7/556 ,  H03G3/30 ,  H04B1/16 ,  H04B1/707

    CPC classification number: G06F7/5235 ,  G06F1/0307 ,  G06F7/483 ,  G06F7/556

    Abstract: PROBLEM TO BE SOLVED: To provide a simplified VGA configuration using the fact that multiplication within a normal numerical domain can be performed by addition within a logarithmic domain.
    SOLUTION: The digital voltage gain amplifier (digital VGA) 132 operates within the logarithmic domain. Properties of the logarithmic domain are exploited to replace the complex multiplier of a conventional VGA 132 with a simple and relatively inexpensive adder 306. Additional techniques are described to significantly reduce the size of one or more lookup-tables LUTs implemented within the digital VGA 132. In this manner, a much more simple, lower-cost design of a digital VGA is achieved.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供简化的VGA配置，使用在正常数值域内的乘法可以通过在对数域内加法来执行的事实。 解决方案：数字电压增益放大器（数字VGA）132在对数域内运行。 利用对数域的属性用简单且相对便宜的加法器306代替常规VGA 132的复数乘法器。描述了附加技术以显着减小在数字VGA 132内实现的一个或多个查找表LUT的大小。 以这种方式，实现了数字VGA的更简单，更低成本的设计。 版权所有（C）2010，JPO＆INPIT

    3.
    发明专利
    未知

    公开(公告)号：BR0114237A

    公开(公告)日：2005-09-06

    申请号：BR0114237

    申请日：2001-09-14

    Applicant: QUALCOMM INC

    Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

    IPC: H03M13/27 ,  H04B1/707 ,  H04L1/00

    Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block 700 provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

    4.
    发明专利
    未知

    公开(公告)号：BR0114238A

    公开(公告)日：2005-08-16

    申请号：BR0114238

    申请日：2001-09-14

    Applicant: QUALCOMM INC

    Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

    IPC: H03M13/27 ,  H04B1/69 ,  H04L1/00

    Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM ( 299, 600 ) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers ( 306 and 307 ) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block ( 700 ) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

    7.
    发明专利
    未知

    公开(公告)号：BR0313835A

    公开(公告)日：2005-08-02

    申请号：BR0313835

    申请日：2003-08-28

    Applicant: QUALCOMM INC

    Inventor： SCHLEGEL NIKOLAI ,  HOLENSTEIN CHRISTIAN ,  FILIPOVIC DANIEL ,  KASTURI NITIN

    IPC: H03D3/00 ,  H04B1/30 ,  H04L25/06

    Abstract: An apparatus for coarse compensation of a direct current (DC) offset in a direct to baseband receiver architecture utilizes a serial analog to digital converter (ADC), such as a Delta-Sigma converter, to convert the received signal to digital form. The output of the ADC is sampled for a predetermined number of samples and a counter coupled to the ADC is incremented each time the sample generated by the ADC is a logic one. The counter is not incremented if the sample from the ADC is a logic zero. After the predetermined number of samples is obtained, the counter value is indicative of the DC offset in the received signal. The counter value may be converted by a code converter to a correction value for easy operation of a digital to analog converter (DAC). If the number of samples from the ADC is a power of two, the code converted may be readily implemented by simply inverting the most significant bit (MSB) from the counter to thereby generate a twos complement version of the counter value. The correction value is coupled to the DAC to generate a compensation signal, which is provided to the received signal path in the form of a feedback signal to compensate for the DC offset.

    Communication system method and apparatus
    9.
    发明专利
    Communication system method and apparatus 未知

    公开(公告)号：AU8903301A

    公开(公告)日：2002-04-15

    申请号：AU8903301

    申请日：2001-09-14

    Applicant: QUALCOMM INC

    Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES Y

    IPC: H03M13/27 ,  H04B1/69 ,  H04L1/00

    Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM ( 299, 600 ) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers ( 306 and 307 ) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block ( 700 ) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

    10.
    发明专利
    未知

    公开(公告)号：AT397327T

    公开(公告)日：2008-06-15

    申请号：AT01979316

    申请日：2001-09-27

    Applicant: QUALCOMM INC

    Inventor： SCHLEGEL NIKOLAI ,  HURT JAMES

    IPC: H04B1/707 ,  H03M13/27 ,  H04J11/00 ,  H04J13/00

    Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

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