-
公开(公告)号：JP2009010959A
公开(公告)日：2009-01-15
申请号：JP2008177384
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture capable of providing the required signal gain and DC offset correction. SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收器架构具有DC环路，用于消除信号分量的DC偏移，提供一系列增益的数字可变增益放大器（DVGA），提供增益控制的自动增益控制（AGC）回路 用于DVGA和RF /模拟电路，以及串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。 版权所有（C）2009，JPO＆INPIT
-
公开(公告)号：JP2012105322A
公开(公告)日：2012-05-31
申请号：JP2011286363
申请日：2011-12-27
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： RANFA SAN , HOLENSTEIN CHRISTIAN , JAFFEE JAMES
CPC classification number: H03D3/008
Abstract: PROBLEM TO BE SOLVED: To provide a circuit that minimizes a DC offset produced by leakage LO signals.SOLUTION: A DC offset cancellation circuit (95, 200, Cs, 180) in a receiver 100 cancels DC offsets caused by leaked LO (local oscillator) signals from a LO signal generator 105. The receiver first calibrates itself by using the DC offset cancellation circuit during a transmit mode. During the calibration, the DC offset cancellation circuit stores the DC offset voltage signal caused by the leaked LO signals. During a receiving mode when the receiver is receiving a signal, the receiver subtracts the stored DC offset voltage signal from the received signal to cancel the DC offsets caused by leaked LO signals.
Abstract translation: 要解决的问题：提供使由泄漏LO信号产生的DC偏移最小化的电路。 解决方案：接收器100中的DC偏移消除电路（95,200，Cs，180）消除由来自LO信号发生器105的泄露的LO（本地振荡器）信号引起的DC偏移。接收机首先通过使用 DC偏移消除电路。 在校准期间，DC偏移消除电路存储由泄露的LO信号引起的DC偏移电压信号。 在接收器接收信号的接收模式期间，接收机从接收信号中减去存储的直流失调电压信号，以消除由泄露的LO信号引起的直流偏移。 版权所有（C）2012，JPO＆INPIT
-
公开(公告)号：JP2010193489A
公开(公告)日：2010-09-02
申请号：JP2010085217
申请日：2010-04-01
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture providing a signal gain and DC offset correction. SOLUTION: The direct downconversion receiver architecture includes: a DC loop to remove DC offset from signal components; a digital variable gain amplifier (DVGA) to provide a range of gains; an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry; and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop is selected based on the operating mode of the DC loop, since these two loops interact with each other. The duration of time the DC loop is operated in an acquisition mode is selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种提供信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收机架构包括：DC信号消除DC偏移的DC环路; 数字可变增益放大器（DVGA）提供一系列增益; 自动增益控制（AGC）回路，为DVGA和RF /模拟电路提供增益控制; 以及串行总线接口（SBI）单元，通过串行总线提供对RF /模拟电路的控制。 基于DC环路的工作模式选择VGA环路的工作模式，因为这两个环路相互交互。 在采集模式下，DC环路工作的持续时间被选择为与采集模式中的DC环路带宽成反比。 版权所有（C）2010，JPO＆INPIT
-
公开(公告)号：JP2010213310A
公开(公告)日：2010-09-24
申请号：JP2010094023
申请日：2010-04-15
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide an architecture of a direct down conversion receiver capable of providing required signal gain and DC offset correction. SOLUTION: The architecture has a DC loop for removing DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing a gain control relating to the DVGA and an RF/analog circuit, and a serial bus interface (SBI) unit for providing control to the RF/analog circuit via a serial bus. Since these two loops perform mutual interaction with each other in design and disposition of the DVGA, an operation mode of the VGA loop is selected based on an operation mode of the DC loop. Within a time period while the DC loop is operating by a capturing mode, selection is made so as to be operated in inverse proportion to a bandwidth of the DC loop in the capturing mode. The control relating to some or all of RF/analog circuits is provided via the serial bus. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机的架构。 解决方案：该架构具有用于从信号分量中去除DC偏移的直流回路，用于提供增益范围的数字可变增益放大器（DVGA），用于执行与增益范围相关的增益控制的自动增益控制（AGC） DVGA和RF /模拟电路以及串行总线接口（SBI）单元，用于通过串行总线向RF /模拟电路提供控制。 由于这两个循环在DVGA的设计和配置中彼此相互作用，所以基于DC循环的操作模式来选择VGA循环的操作模式。 在DC循环通过捕获模式操作的时间段内，选择在捕获模式中与DC环路的带宽成反比地运行。 通过串行总线提供与RF /模拟电路中的一些或全部相关的控制。 版权所有（C）2010，JPO＆INPIT
-
5.发明专利Methods and apparatus for implementing phase rotation at baseband frequency for transmit diversity 有权用于实施基带频率的发射多径相位旋转的方法和装置
公开(公告)号：JP2013243678A
公开(公告)日：2013-12-05
申请号：JP2013119031
申请日：2013-06-05
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： TANG YIWU , HOLENSTEIN CHRISTIAN , MARCO CASSIA , MAHIM RANJAN
CPC classification number: H04B7/0682 , H04L1/0618 , H04L1/08
Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for implementing phase rotation at baseband frequency for transmit diversity.SOLUTION: An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. The primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path performs phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal.
Abstract translation: 要解决的问题：提供用于在基带频率处实现用于发射分集的相位旋转的方法和装置。解决方案：用于实现用于发射分集的基带频率处的相位旋转的装置可以包括主发射信号路径和分集发射信号路径。 主发射信号路径和分集发射信号路径可以接收主发射信号。 分集发射信号路径内的信号选择器在主发射信号处于基带频率时相对于主发射信号执行相位旋转，从而产生分集发射信号。
-
Patent Agency Ranking
公开(公告)号：JP2008295076A
公开(公告)日：2008-12-04
申请号：JP2008177383
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To obtain a direct down converting receiver architecture having a DC loop for removing a DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing gain control relating to the DVGA and RF/analog circuits, and a serial bus interface (SBI) unit for providing control relating to the RF/analog circuits via a serial bus. SOLUTION: The DVGA is to be effectively designed and disposed. Since these two loops mutually performs interaction, an operation mode of the VGA loop is to be selected based on an operation mode of the DC loop. Selection is made so as to be in inverse proportion to bandwidth of the DC loop in a captured mode while the DC loop is operated by the captured mode. Control is to be provided to some or all of the RF/analog circuits via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：为了获得具有用于从信号分量中去除DC偏移的DC回路的直接下变频接收机架构，用于提供增益范围的数字可变增益放大器（DVGA），自动增益控制（AGC） ）环路，用于执行与DVGA和RF /模拟电路相关的增益控制;以及串行总线接口（SBI）单元，用于经由串行总线提供与RF /模拟电路相关的控制。
解决方案：DVGA要有效设计和处理。 由于这两个环路相互进行交互，所以基于DC循环的操作模式来选择VGA环路的操作模式。 在捕捉模式下，直流环路被捕捉模式操作时，进行与直流回路的带宽成反比例的选择。 将通过串行总线向部分或全部RF /模拟电路提供控制。 版权所有（C）2009，JPO＆INPIT
-
公开(公告)号：BRPI0207274B1
公开(公告)日：2016-07-05
申请号：BR0207274
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： RAGHUPATHY ARUN , WALKER BRETT C , HOLENSTEIN CHRISTIAN , SIH GILBERT C , KANG INYUP , SEVERSON MATTHEW L , PETERZELL PAUL E , CHALLA RAGHU , LI TAO
Abstract: "arquitetura de receptor de conversão direta". uma arquitetura de receptor de conversão descendente direta possuindo um loop de dc para remover o offset de dc a partir das componentes de sinal, um amplificador digital de ganho variável (dvga) para prover uma faixa de ganhos, um loop de controle de ganho automático (agc) para prover controle de ganho para o dvga e circuitos de rf/analógico e uma unidade de interface de barramento serial (sbi) para prover controles para os circuitos de rf/analógico através de um barramento serial. o dvga pode ser projetado vantajosamente e localizado como aqui descrito. o modo operacional do loop de vga pode ser selecionado com base no modo operacional do loop de dc, uma vez que estes dois laops interagem um com o outro. a duração de tempo do loop de dc é operada em um modo de aquisição que pode ser selecionado para ser inversamente proporcional à largura de banda do loop de dc no modo de aquisição. os controles para alguns ou todos os circuitos de rf/analógico podem ser providos através do barramento serial.
-
公开(公告)号：CA2723058C
公开(公告)日：2012-12-11
申请号：CA2723058
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
-
公开(公告)号：AU2003223550A1
公开(公告)日：2003-10-27
申请号：AU2003223550
申请日：2003-04-09
Applicant: QUALCOMM INC
Inventor： HOLENSTEIN CHRISTIAN , KANG INYUP , SEVERSON MATTHEW
Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.
-
公开(公告)号：AU2007234638B2
公开(公告)日：2010-07-08
申请号：AU2007234638
申请日：2007-11-23
Applicant: QUALCOMM INC
Inventor： PETERZELL PAUL E , SIH GILBERT C , CHALLA RAGHU , HOLENSTEIN CHRISTIAN , KANG INJUP , LI TAO , WALKER BRETT C , RAGHUPATHY ARUN , SEVERSON MATTHEW L
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.026 seconds)
