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    Spread spectrum multipath demodulator for multichannel communication system
    1.
    发明专利
    Spread spectrum multipath demodulator for multichannel communication system 有权
    用于多通道通信系统的扩展频谱多路解调器

    公开(公告)号：JP2009219125A

    公开(公告)日：2009-09-24

    申请号：JP2009091657

    申请日：2009-04-06

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： LEVIN JEFFREY A

    IPC: H04B1/711 ,  H04B1/7073 ,  H04B1/7075 ,  H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7113 ,  H04B7/26 ,  H04L27/22

    CPC classification number: H04B1/70752 ,  H04B1/70735 ,  H04B1/70753 ,  H04B1/70756 ,  H04B1/708 ,  H04B1/7085 ,  H04B1/7113 ,  H04B2001/70935

    Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for performing the digital receive processing for multiple signals received over the same RF band.
    SOLUTION: Digital RF samples are stored in a RAM queue which is accessed by a searcher and a demodulator. The searcher and the demodulator are preferably located on the same integrated circuit along with the RAM queue. The demodulator demodulates a set of reverse link signals stored within the RAM queue where each reverse link signal is received with a particular time offset and processed using a particular channel code. The searcher periodically searches for reverse link signals not being processed by the demodulator, and for access requests transmitted via the access channel. The searcher preferably searches during the worthy power control groups of each reverse link signal, which corresponds to the two of sixteen power control groups transmitted during a 1/8 rate frame.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于对通过相同RF频带接收的多个信号执行数字接收处理的系统和方法。 解决方案：数字RF样本存储在RAM队列中，RAM队列由搜索器和解调器访问。 搜索器和解调器优选地与RAM队列一起位于同一集成电路上。 解调器解调存储在RAM队列内的一组反向链路信号，其中每个反向链路信号被接收到特定的时间偏移并且使用特定的信道码进行处理。 搜索者周期性地搜索未被解调器处理的反向链路信号，以及用于经由接入信道发送的接入请求。 搜索者优选地在每个反向链路信号的有价值的功率控制组期间搜索，其对应于在1/8速率帧期间传输的十六个功率控制组中的两个。 版权所有（C）2009，JPO＆INPIT

    Method and apparatus for energy estimation in wireless receiver capable of receiving multiple instance of common signal
    2.
    发明专利
    Method and apparatus for energy estimation in wireless receiver capable of receiving multiple instance of common signal 审中-公开
    无线接收机能够接收多个通用信号的能力估算方法与装置

    公开(公告)号：JP2010252364A

    公开(公告)日：2010-11-04

    申请号：JP2010127062

    申请日：2010-06-02

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： LEVIN JEFFREY A ,  RIDDLE CHRISTOPHER C ,  SHERMAN THOMAS R

    IPC: H04B1/7115 ,  H04B1/712 ,  H04B7/26

    CPC classification number: H04B1/7115 ,  H04B1/712

    Abstract: PROBLEM TO BE SOLVED: To provide a remote unit receiver capable of demodulating a plurality of signal instances corresponding to a single remote unit to which a signal is transmitted.
    SOLUTION: A first instance signal is demodulated to generate a first set energy value corresponding to a data value which is likely a first set signal. A second instance signal is demodulated to generate a second set energy value corresponding to a data value which is likely the first set signal. The first and second set energy values are coupled to determine an energy value of the sets coupled subsequently. A first estimated value of the most likely transmitting data value is determined based on the energy value of the sets coupled.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够解调与发送信号的单个远程单元对应的多个信号实例的远程单元接收机。 解决方案：解调第一实例信号以产生对应于可能是第一设置信号的数据值的第一设定能量值。 第二实例信号被解调以产生对应于可能是第一设定信号的数据值的第二设定能量值。 耦合第一和第二设定能量值以确定随后耦合的组的能量值。 基于所耦合的集合的能量值来确定最可能的发送数据值的第一估计值。 版权所有（C）2011，JPO＆INPIT

    Apparatus and method for encoding and computing discrete cosine transform using butterfly processor
    3.
    发明专利
    Apparatus and method for encoding and computing discrete cosine transform using butterfly processor 有权
    使用BUTTERFLY处理器编码和计算离散COSINE变换的装置和方法

    公开(公告)号：JP2013153450A

    公开(公告)日：2013-08-08

    申请号：JP2013029067

    申请日：2013-02-18

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： LAROCCA JUDITH ,  IRVINE CHRIS A ,  LEVIN JEFFREY A

    IPC: G06F17/14 ,  H03M7/30 ,  G06F7/00 ,  G06T9/00 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

    CPC classification number: G06F17/147

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus to determine a transform of a block of encoded data.SOLUTION: The block of encoded data comprises a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor and is configured, if enabled, to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and, if disabled, to transfer a second portion of processed data elements to at least one holding register.

    Abstract translation: 要解决的问题：提供一种确定编码数据块的变换的装置。解码：编码数据块包括多个数据元素。 输入寄存器被配置为接收预定量的数据元素。 至少一个蝶形处理器耦合到输入寄存器，并且被配置为对所选择的数据元素对执行至少一个数学运算，以产生经处理的数据元素的输出。 至少一个中间寄存器耦合到蝶形处理器并且被配置为临时存储经处理的数据。 反馈回路耦合到中间寄存器和蝶形处理器，并且如果启用，则被配置为将经处理的数据元素的第一部分传送到适当的蝶形处理器以执行附加的数学运算，并且如果被禁用，则将第二部分 处理的数据元素至少一个保持寄存器。

    Apparatus and method for encoding and computing discrete cosine transform using butterfly processor
    4.
    发明专利
    Apparatus and method for encoding and computing discrete cosine transform using butterfly processor 有权
    使用BUTTERFLY处理器编码和计算离散COSINE变换的装置和方法

    公开(公告)号：JP2009177802A

    公开(公告)日：2009-08-06

    申请号：JP2008329261

    申请日：2008-12-25

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： LAROCCA JUDITH ,  IRVINE CHRIS A ,  LEVIN JEFFREY A

    IPC: G06F17/14 ,  H04N7/30 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/50

    CPC classification number: G06F17/147

    Abstract: PROBLEM TO BE SOLVED: To provide an efficient DCT (discrete cosine transform) computing circuit of DCT-encoded data. SOLUTION: An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations, and if disabled, is configured to transfer a second portion of processed data elements to at least one holding register. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供DCT编码数据的高效DCT（离散余弦变换）计算电路。

    解决方案：输入寄存器被配置为接收预定量的数据元素。 至少一个蝶形处理器耦合到输入寄存器，并且被配置为对所选择的数据元素对执行至少一个数学运算，以产生经处理的数据元素的输出。 至少一个中间寄存器耦合到蝶形处理器并且被配置为临时存储经处理的数据。 反馈回路耦合到中间寄存器和蝶形处理器，并且如果启用，则被配置为将经处理的数据元素的第一部分传送到适当的蝶形处理器以执行附加的数学运算，并且如果被禁用则被配置为传送第二 处理的数据元素的一部分到至少一个保持寄存器。 版权所有（C）2009，JPO＆INPIT

    LAST FINGER POLLING FOR RAKE RECEIVERS
    6.
    发明申请
    LAST FINGER POLLING FOR RAKE RECEIVERS 审中-公开
    用于RAKE接收器的最近手指轮询

    公开(公告)号：WO2004112272A8

    公开(公告)日：2005-02-17

    申请号：PCT/US2004017160

    申请日：2004-05-28

    Applicant: QUALCOMM INC ,  KINDRED DANIEL R ,  LEVIN JEFFREY A ,  HALTER STEVEN J

    Inventor： KINDRED DANIEL R ,  LEVIN JEFFREY A ,  HALTER STEVEN J

    IPC: H04B1/707

    CPC classification number: H04B1/7117 ,  H04B2201/70707

    Abstract: Techniques for polling fingers on a channel (which are fingers for which symbols are to be combined) to determine the last finger on the channel. As each finger is polled, the polled finger compares its state information with the state information for the channel to determine whether or not it is the last finger on the channel. If the polled finger is deemed as the last finger then, (1) the channel state information is updated with the polled finger state information, and (2) the symbols provided by the polled finger may be marked as being ready for subsequent processing. This avoids buffering the demodulated symbols for a duration time that is longer than the largest expacted difference between the earliest and the latest arriving mutipath components.

    Abstract translation: 用于在通道（其是要组合符号的手指）上轮询手指以确定通道上的最后一个手指的技术。 当轮询每个手指时，被轮询的手指将其状态信息与通道的状态信息进行比较，以确定其是否是通道上的最后一个手指。 如果被轮询的手指被认为是最后一个手指，则（1）通过轮询的手指状态信息来更新信道状态信息，以及（2）被轮询的手指提供的符号可被标记为准备好进行后续处理。 这避免了在最早和最近到达的多径分量之间的最大消耗差之间的持续时间内缓冲解调符号。

    PACKET-BASED PROCESSING SYSTEM
    8.
    发明申请
    PACKET-BASED PROCESSING SYSTEM 审中-公开
    基于分组的处理系统

    公开(公告)号：WO2009026554A3

    公开(公告)日：2009-09-03

    申请号：PCT/US2008074091

    申请日：2008-08-22

    Applicant: QUALCOMM INC ,  IRANINEJAD MEHRABAN ,  LEVIN JEFFREY A ,  CANOY MICHAEL-DAVID N ,  HOWARD MICHAEL ALEXANDER ,  ZIV NOAM A ,  SALVI ROHAN SUDHAKAR

    Inventor： IRANINEJAD MEHRABAN ,  LEVIN JEFFREY A ,  CANOY MICHAEL-DAVID N ,  HOWARD MICHAEL ALEXANDER ,  ZIV NOAM A ,  SALVI ROHAN SUDHAKAR

    IPC: G06F13/38

    CPC classification number: H04W24/02 ,  H04L49/90 ,  H04L69/22 ,  H04W88/02 ,  H04W88/08

    Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.

    Abstract translation: 描述适用于各种应用的基于分组的处理系统，诸如用于无线通信系统中的基站或终端。 基于分组的处理系统可以包括多个处理模块和至少一个传输模块。 处理模块可以通过公共分组接口彼此发送分组，并且可以异步地操作。 传输模块可以转发由处理模块发送的分组，并且可以相对于处理模块异步地操作。 每个处理模块可以包括网络接口，至少一个缓冲器，分组解析器，分组构建器和至少一个处理单元。 每个处理模块可以支持至少一个服务。 每个分组可以包括报头和有效载荷。 报头可以包括用于发送分组的源服务的源服务地址和接收分组的接收方服务的目的地服务地址。

    A METHOD AND APPARATUS FOR COMPRESSING SIGNALS IN A FIXED POINT FORMAT WITHOUT INTRODUCING A BIAS
    9.
    发明申请
    A METHOD AND APPARATUS FOR COMPRESSING SIGNALS IN A FIXED POINT FORMAT WITHOUT INTRODUCING A BIAS 审中-公开
    一种固定点格式压缩信号的方法和装置，不需要引入偏置

    公开(公告)号：WO0010253A3

    公开(公告)日：2000-05-18

    申请号：PCT/US9918546

    申请日：1999-08-13

    Applicant: QUALCOMM INC

    Inventor： RIDDLE CHRISTOPHER C ,  LEVIN JEFFREY A

    IPC: H03M7/24 ,  G06F7/48 ,  H03M7/34 ,  G06F5/01

    CPC classification number: G06F7/48 ,  G06F7/49952 ,  G06F7/49963

    Abstract: A method and apparatus for compressing fixed point signals without introducing a bias. Signals are compressed according to a dithered rounding approach wherein signal values are rounded up and rounded down with approximately equal probability, canceling the bias that would otherwise result from the rounding operation. Numerical properties of the input signal are exploited in order to determine whether the signal value should be rounded up or down. Signal compression may, therefore, be introduced at multiple points within a system without accumulating a signal bias and degrading downstream performance. Further, one bit signal compression may be achieved in a particularly efficient fashion with a minimal amount of hardware.

    Abstract translation: 一种压缩定点信号而不引入偏差的方法和设备。 信号根据抖动舍入方法进行压缩，其中信号值被四舍五入并以近似相等的概率向下取整，从而抵消否则由舍入操作导致的偏差。 利用输入信号的数字特性来确定信号值是应该向上舍入还是向下舍入。 因此，信号压缩可以在系统内的多个点引入，而不会累积信号偏差并降低下游性能。 此外，可以用最少量的硬件以特别有效的方式实现一位信号压缩。

    STATISTICS AND FAILURE DETECTION IN A NETWORK ON A CHIP (NoC) NETWORK
    10.
    发明申请
    STATISTICS AND FAILURE DETECTION IN A NETWORK ON A CHIP (NoC) NETWORK 审中-公开
    网络中的统计和故障检测（NoC）网络

    公开(公告)号：WO2014025621A2

    公开(公告)日：2014-02-13

    申请号：PCT/US2013053293

    申请日：2013-08-01

    Applicant: QUALCOMM INC

    Inventor： RANGAN VENKAT ,  LEVIN JEFFREY A ,  BERAHA RODOLFO G

    IPC: H04L12/26

    CPC classification number: H04L43/106 ,  G06F15/7825 ,  H04L41/0659 ,  H04L41/0668 ,  H04L43/04 ,  H04L43/0852 ,  H04L43/10 ,  H04L43/50

    Abstract: Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.

    Abstract translation: 本公开的某些方面支持用于在芯片上的网络（NoC）中​​收集系统信息的技术。 专用分组可以从源节点发送到目的地节点。 当它通过NoC时，专用分组可以从各个节点收集信息，这些信息可能由目的地节点可用。 收集的信息可用于检测故障并收集有关NoC的统计信息。

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