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公开(公告)号：DK147028B
公开(公告)日：1984-03-19
申请号：DK30675
申请日：1975-01-29
Applicant: RCA CORP
Inventor： STECKLER STEVEN ALAN , LIMBERG ALLEN LEROY
Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.
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公开(公告)号：FI59900C
公开(公告)日：1981-10-12
申请号：FI750169
申请日：1975-01-23
Applicant: RCA CORP
Inventor： STECKLER STEVEN ALAN , LIMBERG ALLEN LEROY
Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.
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公开(公告)号：AU5511673A
公开(公告)日：1974-11-07
申请号：AU5511673
申请日：1973-05-02
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY , CHRISTENSEN ROY MARTIN , GIBSON JAMES JOHN
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公开(公告)号：MY7300380A
公开(公告)日：1973-12-31
申请号：MY7300380
申请日：1973-12-30
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
Abstract: 1,220,955. Video amplifiers; colour television receiver. R.C.A. CORPORATION. 12 June, 1968 [12 June, 1967], No. 27957/68. Headings H3T and H4F. Video amplifiers (e.g. transistors 36, 38, 40) which are A.C. coupled at 66, 68, 70 to the grids 60, 62, 64 of the tube 10 of a T.V. receiver and which have associated D.C. restoring diodes 76, 78, 80 arranged to conduct during retrace intervals, also have a protection circuit incorporating a further diode 102 which is connected between the restoring diodes and a potential source 88 and which is reverse biased by the source 88 during normal receiver operation. Each transistor 36, 38, 40 amplifies either a colour signal or a colour difference signal, the luminance signal in the latter case being applied to cathodes 16, 18, 20. A transistor switch 90 is turned on by line retrace signals 96 to earth collector 90 whereby the potential defined by a divider 84, 86 forward biases the restoring diodes 76, 78, 80 to discharge the capacitors 66, 68, 70 to the defined potential. If arc-over occurs in the tube 10 from high voltage to a grid 60, 62, 64, the protective diode 102 is forward biased and the arc-over surge current is discharged into the supply capacitor 104, thus protecting the transistors 36, 38, 40 from damage.
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公开(公告)号：FI842489A
公开(公告)日：1984-12-28
申请号：FI842489
申请日：1984-06-20
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , G06G
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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Patent Agency Ranking
公开(公告)号：FI842489A0
公开(公告)日：1984-06-20
申请号：FI842489
申请日：1984-06-20
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , G06G
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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公开(公告)号：DE2503887A1
公开(公告)日：1975-07-31
申请号：DE2503887
申请日：1975-01-30
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY , STECKLER STEVEN ALAN
Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.
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公开(公告)号：DE2445134A1
公开(公告)日：1975-03-27
申请号：DE2445134
申请日：1974-09-20
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
Abstract: A first biasing transistor has at least a portion of its base current supplied by the emitter current of a second biasing transistor. The collector current of the first transistor is larger than the collector current of the second transistor by a factor proportional to the hfe current gain characteristic of the first transistor. The collector current of the first transistor is used to establish the quiescent collector-to-emitter current flow of an amplifier transistor having an hfe which matches that of the first biasing transistor. The collector current of the second transistor is used to establish the level quiescent base current supplied to the amplifier for supporting the latter quiescent collector-to-emitter current flow. This avoids quiescent base current drain from the circuitry providing input signal to the amplifier transistor.
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公开(公告)号：AU2955584A
公开(公告)日：1985-01-03
申请号：AU2955584
申请日：1984-06-20
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , H03H17/00
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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