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公开(公告)号：FI863028A
公开(公告)日：1987-01-31
申请号：FI863028
申请日：1986-07-23
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: A trace switch (S H ), operated at a line rate, is coupled to a line deflection winding (L H ) and a trace capacitance (C t ) for applying a trace voltage (V t ) to the deflection winding (L H ) to generate line scanning current in the deflection winding (L H ). A deflection retrace capacitance (C RH ) is coupled to the deflection winding (L H ) for forming a deflection retrace resonant circuit (40) during the line retrace interval to generate a deflection retrace pulse voltage (V R ). A modulator inductance (L m ) is coupled to the trace switch (S H ) and to the line deflection winding (L H ). A modulator switch (S m ) applies a line rate, switched mode, modulation voltage (V m ) directly to the modulator inductance (L m ) to control the amplitude of the current in the modulator inductance (L m ) at the end of the line trace interval. A modulator retrace capacitance (C Rm ) is coupled by the modulator switch (S m ) to the modulator inductance (L m ) during the line retrace interval for forming a modulator retrace resonant circuit (50). The switched mode modulation voltage is varied (42) at a field rate to provide side pincushion correction to the line scanning current (i H ).
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公开(公告)号：FR2585203A1
公开(公告)日：1987-01-23
申请号：FR8610358
申请日：1986-07-16
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: A digital sample rate reduction apparatus receives an input signal occurring at a given sample rate and produces an output signal occurring at a rate which is two-thirds the input sample rate. One half of the output samples are interpolated samples and the other half are original input samples.
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公开(公告)号：GB2141002B
公开(公告)日：1986-11-26
申请号：GB8412562
申请日：1984-05-17
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FUHRER JACK SELIG
IPC: H04N1/405 , G06F17/10 , G06T5/00 , G06T9/00 , H03H17/02 , H03M1/04 , H03M1/20 , H03M7/30 , H03M7/36 , H04N9/64 , H04N11/04 , H04N5/14
Abstract: The present invention provides for the generation of digitally dithered digital signals which can have an apparent quantizing resolution unaffected by truncation of the least significant bit. The truncated digital signal is dithered in an ordered fashion by adding thereto a bit developed in response to one condition of the truncated bit and is not dithered in response to another condition thereof. The original digital signal can be reconstructed by combining successive samples of the truncated digital signals. One feature of the present invention provides a truncation of digital signals.
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公开(公告)号：IT1137795B
公开(公告)日：1986-09-10
申请号：IT2335481
申请日：1981-08-03
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: An inverter coupled to a source of DC input voltage is operated at the horizontal deflection frequency for developing a horizontal rate square-wave supply voltage. A power transformer having a first winding excited by the square-wave supply voltage develops a horizontal rate alternating polarity output voltage across second and third windings. A horizontal deflection generator is coupled to the second winding and is energized thereby to develop a trace voltage across a race capacitor. The deflection generator includes a trace switch coupled across the series arrangement of a horizontal deflection winding, the trace capacitor and the power transformer third winding. The trace switch is operated at a horizontal rate to generate horizontal deflection or scanning current in the deflection winding. A phase control circuit phases the alternating polarity output voltage relative to the phasing of the horizontal scanning current so as to apply a greater magnitude voltage across the horizontal deflection winding during the last half of the trace interval of each deflection cycle than during the first half of the trace interval. In this manner, linearity correction of the horizontal scanning current is obtained.
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公开(公告)号：FI854661A
公开(公告)日：1986-06-04
申请号：FI854661
申请日：1985-11-26
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: a A narrow bandwidth analog-to-digital conversion (ADC) system is described in the context of the color burst processing and burst phase detecting circuitry of a digital color television receiver. The ADC (14) includes a dither generator which adds a dither signal to either the analog input signal (10) or to the reference signal (38) used by the ADC. This dither signal increases in magnitude by 1/16 of an LSB value at a rate one-quarter of the burst frequency and changes in sign at one-half of the burst frequency. This signal passes through a low-pass filter (18) in the chrominance channel providing an increase in sample resolution by averaging the samples in a chroma band-pass filter and in the phase detecting circuitry (30).
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Patent Agency Ranking
公开(公告)号：DE3542104A1
公开(公告)日：1986-05-28
申请号：DE3542104
申请日：1985-11-28
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: A 7 bit digital signal is dithered by adding a low-level digital dithering signal comprised of alternating 1's and 0's, and by truncating the product to 6 bits. To dedither, an EXCLUSIVE-OR gate compares the previous and the current values of the least significant bit of the 6 bit dithered signal. If they are dissimilar, it outputs a "1". Otherwise, it outputs a "0". The output of the EXCLUSIVE-OR gate is ANDed with the dithering signal. If the dithering signal and the output of the EXCLUSIVE-OR gate are both one, then the 6 bit dithered signal is decremented. Otherwise, the 6 bit dithered signal is passed unchanged. The decremented-or-not 6 bit dithered signal is combined with the bit generated by the EXCLUSIVE-OR gate to produce the final 7 bit reconstituted signal.
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公开(公告)号：FI861268A0
公开(公告)日：1986-03-25
申请号：FI861268
申请日：1986-03-25
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: In a synchronized digital horizontal deflection system operating at 2xfH, a digital phase-lock-loop circuit generates first fH rate signal that is synchronized to the horizontal sync pulses, and a second fH rate second signal that is delayed from the first signal by one-half of the period H. A digital phase-control-loop circuit receives the first and second signals and generates a horizontal deflection control signal at 2xfH rate that controls the retrace interval timing in a deflection circuit output stage. The synchronization of every other retrace interval occur in accordance with information provided by the first signal.
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公开(公告)号：HK16886A
公开(公告)日：1986-03-14
申请号：HK16886
申请日：1986-03-06
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , HICKS JAMES EDWARD
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公开(公告)号：FI860558A
公开(公告)日：1986-02-07
申请号：FI860558
申请日：1986-02-07
Applicant: RCA CORP
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公开(公告)号：MY8500778A
公开(公告)日：1985-12-31
申请号：MY8500778
申请日：1985-12-30
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , HICKS JAMES EDWARD
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