4.
    发明专利
    未知

    公开(公告)号:FI871534A

    公开(公告)日:1987-10-16

    申请号:FI871534

    申请日:1987-04-08

    Applicant: RCA CORP

    Abstract: A vertical deflection amplifier (20) of a video display apparatus includes first (Q1) and second (Q2) transistor amplifier output stages arranged in a totem-pole, push-pull configuration. A vertical-deflection winding (LV) is coupled to the output stages at a deflection amplifier output terminal (22). An S-capacitor (C1) is coupled to the deflection winding (LV) at a second terminal (21) remote from the output terminal (22). A source (23) of deflection rate signals is coupled to the deflection amplifier (20) for generating a deflection current (iv) in the deflection winding (LV). A base current generating circuit (40) is coupled to one (Q1) of the transistor amplifier output stages for providing base current (i1) thereto. The S-capacitor voltage (V1) is applied to the base current generating circuit (40) for enabling conduction of base current (i1) in the one amplifier output stage (Q1). When the video display apparatus is first turned on, the initially discharged S-capacitor (C1) is slowly charged from a DC voltage supply (+30V) to delay generation of vertical def lection past completion of picture tube degaussing. A DC power supply (16) upon energization in response to a switch (15) produces a DC level (+DC2) sufficient for operating the deflection amplifier prior to the conclusion of degaussing.

    5.
    发明专利
    未知

    公开(公告)号:FI871534A0

    公开(公告)日:1987-04-08

    申请号:FI871534

    申请日:1987-04-08

    Applicant: RCA CORP

    Abstract: A vertical deflection amplifier (20) of a video display apparatus includes first (Q1) and second (Q2) transistor amplifier output stages arranged in a totem-pole, push-pull configuration. A vertical-deflection winding (LV) is coupled to the output stages at a deflection amplifier output terminal (22). An S-capacitor (C1) is coupled to the deflection winding (LV) at a second terminal (21) remote from the output terminal (22). A source (23) of deflection rate signals is coupled to the deflection amplifier (20) for generating a deflection current (iv) in the deflection winding (LV). A base current generating circuit (40) is coupled to one (Q1) of the transistor amplifier output stages for providing base current (i1) thereto. The S-capacitor voltage (V1) is applied to the base current generating circuit (40) for enabling conduction of base current (i1) in the one amplifier output stage (Q1). When the video display apparatus is first turned on, the initially discharged S-capacitor (C1) is slowly charged from a DC voltage supply (+30V) to delay generation of vertical def lection past completion of picture tube degaussing. A DC power supply (16) upon energization in response to a switch (15) produces a DC level (+DC2) sufficient for operating the deflection amplifier prior to the conclusion of degaussing.

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