公开(公告)号：JP2008060704A

公开(公告)日：2008-03-13

申请号：JP2006232424

申请日：2006-08-29

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KOTANI YASUTAKA

IPC: H04L9/08

Abstract: PROBLEM TO BE SOLVED: To obtain secure communication by an easy operation.
SOLUTION: When an operation of a printer 12 to print data of an image picked up by a digital camera 11 is performed on an operation part 41, a common key for use in encryption of image data is generated. The generated common key, a detection code for detecting a transmission error of the common key, and a control signal indicating print processing are transmitted to the printer 12 by infrared communication. The image data is encrypted by the generated common key and is transmitted to the printer 12 by wireless LAN communication. This invention is applicable to a communication system wherein data is transmitted from a transmission-side device and prescribed processing using the data is performed in a reception-side device.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过简单的操作获得安全的通信。 解决方案：当在操作部分41上执行打印机12的打印由数字照相机11拾取的图像的数据的操作时，产生用于加密图像数据的公共密钥。 所产生的公共密钥，用于检测公共密钥的传输错误的检测码和指示打印处理的控制信号通过红外通信传送到打印机12。 图像数据由所生成的公共密钥加密，并通过无线LAN通信被发送到打印机12。 本发明可应用于其中从发送侧装置发送数据的通信系统，并且在接收方装置中执行使用该数据的规定处理。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003023352A

公开(公告)日：2003-01-24

申请号：JP2001208348

申请日：2001-07-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMURA TAKAYA ,  YAMAOKA SHINSUKE ,  KOTANI YASUTAKA ,  OSABE HISAO

IPC: G11B20/10 ,  G11B20/14 ,  H03L7/06 ,  H03L7/08 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a clock regeneration circuit in which frequency synchronization can be performed without exerting an adverse influence upon a clock regeneration part. SOLUTION: The clock regeneration circuit is provided with clock regeneration means (1-8) and frequency detecting means (9-14) and by using an edge counter 11 for frequency detection for frequency synchronization, error output provided by a digital controller oscillator(DCO) 8 and the edge counter 11 becomes a 0th-order error not to be integrated. Even when a phase shift occurs in a regenerated clock, just a single frequency occurs and errors do not continuously occur.

Abstract translation: 要解决的问题：提供一种时钟再生电路，其中可以执行频率同步而不对时钟再生部分产生不利影响。 解决方案：时钟再生电路设有时钟再生装置（1-8）和频率检测装置（9-14），并通过使用用于频率同步的频率检测的边沿计数器11，由数字控制振荡器（DCO）提供的误差输出 ）8，并且边缘计数器11变为不被积分的零级误差。 即使当在再生时钟中发生相移时，仅发生单个频率并且不会连续发生错误。

公开(公告)号：JP2001118228A

公开(公告)日：2001-04-27

申请号：JP29592899

申请日：1999-10-18

Applicant: SONY CORP

Inventor： HIMENO TAKUJI ,  KOTANI YASUTAKA ,  OTA SHUICHI

IPC: G11B5/53

Abstract: PROBLEM TO BE SOLVED: To reduce the manufacturing cost of a device for recording video data by forming a track out of an AP format and an LP format. SOLUTION: After a substrate track TR3 is recorded by a first recording head in a position ahead by one track pitch of the recording position of a second recording head, when overwriting tracks TR4SP and TR4LP are recorded in the recording position by the second recording head, the height positions of the first and second recording heads are adjusted so as to set the amount of deviation between the track center lines C4SP and C4LP of the overwriting tracks TR4SP and TR4LP recording with an SP format and the boundary lines of substrate tracks TR3 and TR1 equal to the amount of deviation between the track center lines 4SP and 4LP of the overwriting tracks TR4SP and TR4LP recorded with an LP format and the boundary lines of the substrate tracks TR1 and TR3, and thus recording can carried out on both of the LP and SP formats.

公开(公告)号：JPH0983357A

公开(公告)日：1997-03-28

申请号：JP25712295

申请日：1995-09-08

Applicant: SONY CORP

Inventor： SEKINE MASATO ,  KOTANI YASUTAKA ,  MIYAGI SHIRO

IPC: G11B20/14 ,  H03L7/08 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To make a PLL circuit immune to noise and to stabilize characteristics concerning the PLL circuit to be used as a reproducing clock generating circuit for a digital signal reproducing device. SOLUTION: The compared output of a phase comparator 3 is outputted in the form of a balanced (differential) signal and supplied to a loop filter 4, and the output signal of the loop filter 4 is supplied to the control voltage input terminal of a VCO 5 in the form of the balanced signal. The in-phase component of noise contained in a control voltage can be canceled. Besides, the charging and discharging currents of a capacitor at the loop filter flow through the same conductive type of transistor and the characteristics of the PLL circuit can be prevented from being degraded by difference in the characteristics of elements.

公开(公告)号：JPH05167350A

公开(公告)日：1993-07-02

申请号：JP35287491

申请日：1991-12-17

Applicant: SONY CORP

Inventor： KOTANI YASUTAKA ,  MIYAGI SHIRO

IPC: H03C3/00 ,  H04N5/92 ,  H04N5/922

Abstract: PURPOSE:To decrease the generation of moire by preventing the secondary distortion of a circuit in the rear step of the FM modulator by generating FM signals, in which a third-order higher harmonic wave component is not contained, without using any element to be operated at high speed. CONSTITUTION:Rectangular wave signals are generated by oscillating a main body 1 of the FM modulator at a frequency corresponding to the value of signals having waves to be modulated, and a trapezoidal wave generating circuit 2 generates a vertically symmetric trapezoidal wave signal, for which the ratio of a flat part is '1/6' to one cycle, based on this rectangular wave signal. This trapezoidal wave signal is outputted as the FM signal corresponding to the signal to be modulated.

公开(公告)号：JPH04172660A

公开(公告)日：1992-06-19

申请号：JP30160690

申请日：1990-11-07

Applicant: SONY CORP

Inventor： KOTANI YASUTAKA

IPC: G11B20/06

Abstract: PURPOSE:To accurately control carriers of a plurality of FM modulators by operating the modulators as a function of a voltage controlled oscillator (VCO) in a PLL, and operating the modulators by the PLL. CONSTITUTION:An FM modulator is composed of phase-locked loop (PLL) control type FM modulators 20, 21, and an FM modulation signal is modulated by using a clock divided in frequency by the ratio of integer multiples of a certain clock. That is, the modulator 20 (21) is composed of an FM modulator 201, a frequency divider 202 having 1/M of frequency dividing ratio, a frequency divider 203 having 1/N of frequency dividing ratio, a phase comparator 204, and a low pass filter 206 connected thereto to use the fact that the modulator 201 is operated as a function of a VCO. Thus, a difference of the carriers of the modulators is very reduced, and accurate FM modulation is performed by a simple circuit configuration.

公开(公告)号：JP2006314078A

公开(公告)日：2006-11-16

申请号：JP2006036655

申请日：2006-02-14

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KAWADA SHIYOUGO ,  URUSHIBARA TOSHICHIKA ,  SEKIGUCHI MASAMI ,  KOTANI YASUTAKA

IPC: H04N5/225 ,  H04R1/40 ,  H04R3/00 ,  H04R5/027

CPC classification number: H04N5/232 ,  H04N5/23296

Abstract: PROBLEM TO BE SOLVED: To reproduce voice with high presence by voice recording of multi-channels, and to clearly reproduce the voice generated by a subject aimed. SOLUTION: Sound collection signals collected by a wireless microphone mounted to the subject are transmitted to a video camera 30, in a wireless manner. In the video camera 30, a multi-channel sound collection processing part 35 collects voice by a plurality of microphones 35a to 35d, and a multi-channel voice synthesis part 37 generates a multi-channel voice signal, based on each voice signal. Together with this, the sound collection signals from the wireless microphone are received, and the multi-channel voice synthesis part 37 assigns sound collection signals to one or more arbitrary channels of the multi-channel voice signal, synthesizes them with each arbitrary synthesis ratio, and records them to a recording medium together with an imaging image signal. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过多声道的语音记录来再现具有高存在性的声音，并且清楚地再现由被摄体产生的声音。 解决方案：由安装到被摄体的无线麦克风收集的声音收集信号以无线方式传送到摄像机30。 在摄像机30中，多声道声音采集处理部35通过多个麦克风35a〜35d收集语音，多声道语音合成部37基于各声音信号生成多声道语音信号。 接收来自无线麦克风的声音采集信号，多声道语音合成部37将声音收集信号分配给多声道语音信号的一个或多个任意声道，以每个任意的合成比合成它们， 并将其与成像图像信号一起记录到记录介质。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003078409A

公开(公告)日：2003-03-14

申请号：JP2001262065

申请日：2001-08-30

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMURA TAKAYA ,  YAMAOKA SHINSUKE ,  KOTANI YASUTAKA ,  OSABE HISAO

IPC: G11B20/14 ,  H03L7/091 ,  H03L7/113 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a phase detecting method, a phase detecting circuit and a phase synchronizing device capable of performing frequency pulling by obtaining a differential value of a phase error even without performing exception handling. SOLUTION: This phase detecting method is provided with a detection step for detecting two sampling phases that sandwich zero cross among sampling phases, an interpolation step for interpolating and calculating a signal level of an intermediate phase of the two sampling phases, an addition step for adding the intermediate phase as a sampling phase, and a repeating step for repeating the detection step, the interpolation step, and the addition step N (N is a natural number) times, in order to detect phases of an electric signal, so that a stable phase error output can be obtained without signal level dependence by interpolating a signal level between sampling phases and calculating a zero cross phase of a signal and frequency pulling capability of phase synchronous processing is improved and frequency pulling processing is simplified.

Abstract translation: 要解决的问题：为了提供相位检测方法，相位检测电路和相位同步装置，即使不进行异常处理也能够通过获得相位误差的差分值来执行频率牵引。 解决方案：该相位检测方法具有用于检测采样相位之间夹杂零交叉的两个采样相位的检测步骤，用于内插和计算两个采样相位的中间相位的信号电平的插值步骤，添加步骤 中间相作为采样相位，以及重复步骤，用于重复检测步骤，插值步骤和相加步骤N（N为自然数）次，以检测电信号的相位，使得稳定的 可以通过内插采样相位之间的信号电平并计算信号的零交叉相位来获得相位误差输出，而不需要信号电平依赖性，并且提高了相位同步处理的拉频能力，并简化了频率拉伸处理。

公开(公告)号：JP2002216422A

公开(公告)日：2002-08-02

申请号：JP2001007487

申请日：2001-01-16

Applicant: SONY CORP

Inventor： KOTANI YASUTAKA ,  OSABE HISAO

IPC: G11B5/09 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To improve the accuracy of waveform equalization in the preceding stage of a PLL(phase locked loop). SOLUTION: The waveform equalization of the data of a magnetic recording medium 11 read by a magnetic head 12 is performed by an equalizer 41. A phase frequency detecting part 18 and a VCO(voltage controlled oscillator) 19 constitutes a so-called PLL. A CPU 42 calculates an optimum tap coefficient by using an LMS(least mean square) algorithm on the basis of the output of an A/D conversion part 15, and outputs it to a digital equalizer 16. Based on the calculated tap coefficient, the CPU 42 produces further a control signal for optimizing the equalization characteristics of waveform equalization of the equalizer 41, and outputs it to the equalizer 41. The digital equalizer equalizes a reproducing signal by using the tap coefficient inputted from the CPU 42. The equalizer 41 applies waveform equalization to the inputted signal on the basis of the control signal inputted from the CPU 42.

公开(公告)号：JP2001291334A

公开(公告)日：2001-10-19

申请号：JP2000102129

申请日：2000-04-04

Applicant: SONY CORP

Inventor： TAUCHI YOICHIRO ,  KOTANI YASUTAKA ,  KOZAI TOSHINORI

IPC: H04N5/7826 ,  G11B5/008 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/032 ,  G11B27/036 ,  G11B27/30 ,  H04N5/92 ,  H04N9/79 ,  H04N9/804 ,  H04N9/806 ,  H04N9/82

Abstract: PROBLEM TO BE SOLVED: To allow recording of data of HD video signals on a magnetic tape. SOLUTION: The respective tracks formed to incline in a longitudinal direction of the magnetic tape are segmented two sub-tracks through ITG. Preambles are formed at the tops of the respective sub-tracks. Next, main sectors and sub-code sectors are continuously formed without forming gaps between both. Post ambles are formed next to the sub-code sectors. The data of the HD video signals, aural data, data for search, AUX data, etc., are recorded in the main sectors.