公开(公告)号：JPS61206919A

公开(公告)日：1986-09-13

申请号：JP4623985

申请日：1985-03-08

Applicant: SONY CORP

Inventor： OKUBO KENICHI ,  HAGA SHUICHI ,  YAZAWA KENJI ,  OHASHI MITSUO

IPC: G11B5/66 ,  G11B5/64 ,  G11B5/72 ,  G11B5/725 ,  G11B5/73 ,  G11B5/738 ,  G11B5/82

Abstract: PURPOSE:To improve synergistically the durability of a magnetic layer by combining a carbon protective film and a thin film consisting of a solid lubricating agent. CONSTITUTION:An Al-Mg alloy substrate 1 on which an Ni-P plating layer 2 is formed as a nonmagnetic metallic underlying layer is prepd. and an underlying film 3 of low m.p. metal is formed on the layer 2 by vapor deposition of Bi using an electron beam. A thin magnetic metallic film 4 is further formed thereon by the vapor deposition of Co by the electron beam. The carbon protective film 5 is formed thereon by a vacuum deposition method. The thin film 6 consisting of the solid lubricating agent is formed in succession thereto by sputtering in a gaseous argon atmosphere.

公开(公告)号：JP2010171115A

公开(公告)日：2010-08-05

申请号：JP2009010788

申请日：2009-01-21

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OKUBO KENICHI

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To form an LDD (Lightly Doped Drain) diffusion layer for a highly pressure-resistive transistor for forming a source/drain region of an offset structure without the need for additional steps.
SOLUTION: An electrode forming film 41 having a first insulating film 42 on its upper surface is formed on a semiconductor substrate 11 via a gate insulating film 21. A first gate electrode 22 and a plurality of dummy patterns 51 disposed along both sides of the first gate electrode apart from each other are formed by the electrode forming film 41. The first LDD diffusion layers 23, 24 are formed in the semiconductor substrate 11 by ion implantation using the first gate electrode 22 and the dummy patterns 51 as masks. First sidewalls 25 are formed on a sidewall of the first gate electrode 22, on sidewalls of the dummy patterns 51, between the first gate electrode 22 and each dummy pattern 51 and between the respective dummy patterns 51. First source/drain regions 26, 27 are formed on the semiconductor substrate 11 using the first gate electrode 22, each dummy pattern 51 and each first sidewall 25 as masks.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：形成用于形成偏移结构的源极/漏极区域的高耐压晶体管的LDD（轻掺杂漏极）扩散层，而不需要额外的步骤。 解决方案：通过栅极绝缘膜21在半导体衬底11上形成在其上表面上具有第一绝缘膜42的电极形成膜41.第一栅电极22和沿着两侧设置的多个虚设图案51 通过电极形成膜41形成第一栅电极。通过使用第一栅电极22和伪图案51作为掩模的离子注入，在半导体衬底11中形成第一LDD扩散层23,24。 第一侧壁25形成在第一栅电极22的侧壁上，虚设图案51的侧壁，第一栅极电极22和每个虚设图案51之间以及各虚设图案51之间。第一源极/漏极区域26,27 使用第一栅极22，每个虚设图形51和每个第一侧壁25作为掩模形成在半导体基板11上。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2003017690A

公开(公告)日：2003-01-17

申请号：JP2001198778

申请日：2001-06-29

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OKUBO KENICHI

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To easily micronize the channel length of a transistor.
SOLUTION: A first impurity polycrystal semiconductor film 11 composed of polysilicon containing impurities and a first insulation film 12 are formed on a semiconductor substrate 10. Then, the first insulation film 12 and the first impurity polycrystal semiconductor film 11 are opened by a prescribed pattern and an opening 13 is provided. Then, from the opening 13, ion implantations 15a and 15b are obliquely performed. By the oblique ion implantations 15a and 15b, a region 16c where ions are not implanted is formed at the center of the semiconductor substrate 10 in the opening 13. Then, a sidewall spacer 17 is formed at the opening 13 and a gate electrode 19 is formed.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了容易地微细化晶体管的沟道长度。 解决方案：在半导体衬底10上形成由多晶硅含有杂质构成的第一杂质多晶半导体膜11和第一绝缘膜12.然后，第一绝缘膜12和第一杂质多晶半导体膜11以规定的图案打开， 设有开口13。 然后，从开口部13倾斜地进行离子注入15a，15b。 通过倾斜离子注入15a和15b，在开口13中的半导体衬底10的中心处形成没有注入离子的区域16c。然后，在开口13处形成侧壁间隔物17，栅电极19是 形成。

公开(公告)号：JP2002050694A

公开(公告)日：2002-02-15

申请号：JP2000177214

申请日：2000-06-13

Applicant: SONY CORP

Inventor： OKUBO KENICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which the collector layer is made thin, without complicating the processes, and the frequency characteristics are enhanced by decreasing the base take-out resistance. SOLUTION: The method for manufacturing a semiconductor device comprises a step of forming a collector region 3 inside semiconductor substrates 1, 2, a step for thermally oxidizing the semiconductor substrate to form an isolation oxide film 4, a step for forming a first insulation film 7, a step of removing the first insulation film and the isolation oxide film from an emitter forming region to form a recess 2a on the surface of the semiconductor substrate, a step of forming a base region 14 of conductor layer at least in the recess, a step of forming a second insulation film 15 having an opening on a base region, a step of forming an emitter electrode 8 in the opening of the second insulation film, and a step of forming an emitter region 9 by diffusing impurities into the base region from the emitter electrode.

公开(公告)号：JP2000068938A

公开(公告)日：2000-03-03

申请号：JP12760499

申请日：1999-05-07

Applicant: SONY CORP

Inventor： YOSHIDA HIDEKI ,  CHOKAI YOICHI ,  HORIE KAZUYOSHI ,  OKUBO KENICHI ,  SHINO KUNINORI

IPC: H04B10/60 ,  H04B10/00 ,  H04B10/035 ,  H04B10/077 ,  H04B10/079 ,  H04B10/293 ,  H04B10/40 ,  H04B10/50 ,  H04B10/564 ,  H04B10/572 ,  H04B10/69 ,  H04B10/14 ,  H04B10/04 ,  H04B10/06 ,  H04B10/24 ,  H04B10/26 ,  H04B10/28

Abstract: PROBLEM TO BE SOLVED: To obtain an optical transmitter-receiver that surely conducts optical communication by using an optical transmission medium between optical transmitter-receiver sets under an optimum condition. SOLUTION: A control means 2 in an optical transmitter-receiver 20 (21) that connects to an opposite optical transmitter-receiver 21 (20) via optical transmission media F1, F2 to communicate a data signal to the opposite optical transmitter-receiver 21 (20) adjusts a parameter of a light emission power control signal s2C so that the intensity of an optical signal 200 outputted from a light emitting element 4 increases when detection means 8, 9 detect dissidence and selection means 1, 17 set a parameter of a current light emission power control signal s2C as a parameter when the detection means detect coincidence.

公开(公告)号：JP2000019359A

公开(公告)日：2000-01-21

申请号：JP18751798

申请日：1998-07-02

Applicant: SONY CORP

Inventor： YOSHIDA HIDEKI ,  CHOKAI YOICHI ,  HORIE KAZUYOSHI ,  OKUBO KENICHI ,  SHINO KUNINORI

IPC: G02B6/42 ,  H01S5/00 ,  H01S5/30

Abstract: PROBLEM TO BE SOLVED: To provide an optical transmitter-receiver capable of preventing the leakage of light beam to the outside even when an optical fiber is taken off, preventing the entering of dust, etc., to the inside and simply performing self- diagnosis. SOLUTION: This optical transmitter-receiver 100 is provided with a light reception/emission part 150 provided with a light emission means 10A emitting a first optical signal FS to be transmitted, and a light reception means 11A receiving a second optical signal ES of the other side sent through the optical fiber, a control means 200 controlling so as to output the first optical signal FS from the light emission means 10A, an optical fiber hold part 300 opening when the optical fiber 1 is inserted, exposing the end part 1A of the optical fiber 1 to the light reception/emission part 150 side, closing when the optical fiber 1 is pulled out and guiding the first optical signal FS to the light emission means 10A when the first optical signal FS is emitted and a detection means 6 detecting whether or not the optical fiber 1 is inserted into the hold part.

公开(公告)号：JPH11194229A

公开(公告)日：1999-07-21

申请号：JP167498

申请日：1998-01-07

Applicant: SONY CORP

Inventor： HORIE KAZUYOSHI ,  CHOKAI YOICHI ,  YOSHIDA HIDEKI ,  OKUBO KENICHI ,  SHINO KUNINORI

IPC: G02B6/26 ,  G02B6/32

Abstract: PROBLEM TO BE SOLVED: To vary the connection angle of an optical fiber without lowering coupling efficiency. SOLUTION: A 1st optical fiber is coupled with a 1st case 101. A 2nd optical fiber is coupled with a 2nd case 102. The 1st case 101 and 2nd case 102 are coupled rotatably to form a main body case 100. An optical transmission mechanism part 103 is arranged so that its optical axis 105 is aligned with the rotary shaft and light signals are transmitted between the 1st and 2nd optical fibers.

公开(公告)号：JPH1174280A

公开(公告)日：1999-03-16

申请号：JP23454197

申请日：1997-08-29

Applicant: SONY CORP

Inventor： OKUBO KENICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To provide a method through which base and emitter regions can be formed through a fewer number of processes, as compared with the conven tional method without deteriorating the withstand voltage at the junction of a bipolar transistor element. SOLUTION: A method for forming base region and emitter region comprises a process for forming an opening 14 for exposing the outer edge section of a base-forming region into a ring-like state by patterning a photoresist film 12 and a ring-like recessed section 16 by etching the outer edge section of the base forming region, a process for forming an oxide film 18, and a process for exposing an region 20, including the recessed section 16 by patterning a photoresist film 22 and introducing a first impurity of a second conductivity which is opposite to that of a substrate. The method also comprises a process for forming a base region 28 by heat-treating the first impurity, a process for forming an opening 34 for exposing an emitter-forming region in a base region by patterning a photoresist film 32 and introducing a second impurity of the first conductivity to the emitter-forming region, and a process for forming an emitter region 30 by heat-treating the second impurity.

公开(公告)号：JPH1012754A

公开(公告)日：1998-01-16

申请号：JP16121096

申请日：1996-06-21

Applicant: SONY CORP

Inventor： OKUBO KENICHI

IPC: H01L21/76 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To simplify the manufacture process of the semiconductor device constituted by providing a bipolar transistor, a MIS transistor, a capacity element, etc., on the same semiconductor substrate. SOLUTION: After collectors 101 and 102 and a base 103 are formed in a first area 100 of the semiconductor substrate 40, a capacity dielectric film 305 is formed on the semiconductor substrate 40 in a 3rd area 300. An infer-layer insulating film 44 which has an opening above a second area 200 is formed on the semiconductor substrate 40 and a gate insulating film 202 is formed on an exposed surface of the semiconductor substrate 40. The center part of a base 103 and the infer-layer insulating film 44 on the 3rd area 300 are removed after a polysilicon film 45 is formed on the semiconductor substrate 40, the polysilicon film 45, infer-layer insulating film 44, and gate insulating film 202 are patterned to form an emitter electrode 104 in the first area 100, a gate electrode 203 in the second area 200, and an upper electrode 306 on the capacity dielectric film 305 in the third area 300. Then impurities for forming a source and a drain are injected into the second area 200 and an emitter is formed by impurity diffusion from an emitter electrode 104.

公开(公告)号：JPH09148338A

公开(公告)日：1997-06-06

申请号：JP31091195

申请日：1995-11-29

Applicant: SONY CORP

Inventor： OKUBO KENICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor having improved frequency response in which an insulating layer is formed under its base region, but not immediately under its emitter region, so that the collector-base contact area can be reduced without reducing the device size while preventing the decrease in junction breakdown strength. SOLUTION: A substrate 2 includes a buried collector region 3, and a collector contact region 6 formed above the buried collector and connected with it. A base region 4 formed in an upper layer includes an emitter region 5, and an insulating layer 8 is formed under the base region 4, not immediately under the emitter region 5. According to this structure, the area of the base-collector junction between the buried collector region 3 and the base region 4 is substantially reduced. As a result, the collector-base capacitance is reduced, and frequency response is improved.