公开(公告)号：JPS63239958A

公开(公告)日：1988-10-05

申请号：JP7316487

申请日：1987-03-27

Applicant: SONY CORP

Inventor： SAKAMOTO YASUHIRO ,  ONO YOSHIKATSU ,  YAMOTO HISAYOSHI

IPC: B41F17/36 ,  H01L21/56

Abstract: PURPOSE:To prevent breakdown of a protective film at the time of molding, by forming a protective film material layer on the surface of a semiconductor element by a printing method, heating and hardening the protective film material layer, smoothing the hardened protective film material layer so as to form a protective film, and thereafter performing resin packaging. CONSTITUTION:After a protective film material layer 18 is formed on the surface of each semiconductor element 14 by a printing method, the protective film material layer 18 is heated and hardened. Then the hardened protective film material layer 12 is smoothed so as to obtain a protective film 21. Thereafter, resin packaging is performed. for example, each recess part 16 in an original plate 15 for intaglio printing is filled with the protective film material 17, in which polyimide is dissolved in N- methylpyrrolidone. The original plate 15 is rotated and brought into contact with the surface of a semiconductor wafer 13. Thus the protective film material layer 18 is formed on each semiconductor integrated circuit element part 14. Then, the semiconductor wafer 13 is mounted on a heater 19 and heated. Solvent is evaporated from the protective film material layer 18 and hardened, and the polyimide layer 12 is formed. Then the polyimide layer 12, which is in the middle of hardening, is rolled with a roller 22, and the surface is smoothed.

公开(公告)号：JPS63137469A

公开(公告)日：1988-06-09

申请号：JP28515086

申请日：1986-11-29

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  SAKAMOTO YASUHIRO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11

Abstract: PURPOSE:To reduce the occupying area readily, by arranging semiconductor layers of a CMOS inverter continuously and orthogonally at a PMOSFET and an NMOSFET so that source and drain regions of a transfer gate and the drain of the NMOSFET are commonly used. CONSTITUTION:A semiconductor layer 2 has a CMOS inverter region and a transfer gate region. In the CMOS inverter, a semiconductor layer 2a having a pattern width l1 is used for a PMOSFET, and a semiconductor layer 2b having a pattern width l1 is used for an NMOSFET. The MOSFETs are intersected at a right angle and form the continuous semiconductor layer. In the NMOSFET, a semiconductor layer region 13sd becomes source and drain regions, which can be connected to bit lines with an extending part 2c. The output part of the CMOS inverter is arranged at a position, which can be readily continued to the transfer gate. The region 13sd is formed in continuation with said output part of the CMOS inverter. The source and drain regions of the transfer gate are commonly used as the drain of the NMOSFET.

公开(公告)号：JPS63137467A

公开(公告)日：1988-06-09

申请号：JP28514586

申请日：1986-11-29

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  SAKAMOTO YASUHIRO

IPC: H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/786

Abstract: PURPOSE:To reduce the occupying area of a cell readily, by continuously arranging the semiconductor layer and the gate electrode of a CMOS inverter at a PMOSFET and an NMOSFET together so that they are crossed at a right angle. CONSTITUTION:On an insulating substrate 1, a P-type semiconductor layer 2, which is extended in the direction Y with a pattern width l1, is provided; and an N-type semiconductor layer 3, which is extended in the direction X with a pattern width l1, is also provided. The layers 2 and 3, which comprise a thin film semiconductor layer as a unitary body, is divided at a P-N junction part 4 based on the conductivity types. The layer 2 is used as a PMOSFET. The layer 3 is used as an NMOSFET. A contact hole 6 is formed in an interlayer insulating film on the P-N junction part 4. With the connecting part of the PMOSFET and the NMOSFET as an output lead-out point, the output of a CMOS inverter is taken out.

公开(公告)号：JP2002158172A

公开(公告)日：2002-05-31

申请号：JP2001244163

申请日：2001-08-10

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  NAKAJIMA HIDEHARU ,  USUI SETSUO ,  SAKAMOTO YASUHIRO ,  MORI YOSHIFUMI

IPC: G02F1/1368 ,  H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor thin film, and its forming method and system, drawing a clear line of demarcation against a conventional polycrystalline thin film and suitable for fabricating a high performance device having stabilized characteristics in a short time. SOLUTION: At the single crystallization of a non-single crystal thin film, conditions of heat treatment, e.g. laser irradiation, are set such that polycrystalline particles are arranged substantially regularly on an insulating substrate 31 and heat treatment is performed while keeping a surface state where polycrystalline particles are arranged substantially regularly thus forming a single crystal thin film 34 having a structure of advanced crystallization.

公开(公告)号：JP2576496B2

公开(公告)日：1997-01-29

申请号：JP7316387

申请日：1987-03-27

Applicant: SONY CORP

Inventor： YAMOTO HISAYOSHI ,  KIZAKIHARA TOSHIRO ,  SAKAMOTO YASUHIRO ,  ONO YOSHIKATSU

IPC: H01L21/312 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/31 ,  H01L27/10 ,  H01L27/108

公开(公告)号：JP2535890B2

公开(公告)日：1996-09-18

申请号：JP7316187

申请日：1987-03-27

Applicant: SONY CORP

Inventor： YAMOTO HISAYOSHI ,  KIZAKIHARA TOSHIRO ,  SAKAMOTO YASUHIRO ,  ONO YOSHIKATSU

IPC: H01L21/312 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

公开(公告)号：JPS6435965A

公开(公告)日：1989-02-07

申请号：JP19077787

申请日：1987-07-30

Applicant: SONY CORP

Inventor： SAKAMOTO YASUHIRO

IPC: H01L29/80 ,  H01L29/201

Abstract: PURPOSE:To perform a high speed operation of a FET by utilizing a resonance tunnel effect. CONSTITUTION:A predetermined voltage is applied to a source S, and first and second drains D1, D2, and a predetermined voltage is applied to a gate G to move charge from a charge storage layer LS to quantum well channel layers LW1, LW2 by means of a resonance tunnel operation which penetrates the thicknesses of potential barrier layers LB1, LB2 under a gate electrode 1G. Accordingly, charge running times to the layers LW1, LW2, i.e., the first and second drains become very short for the charge required to substantially tunnel the extremely thin layers LB1, LB2. Thus, an ultrahigh speed operation can be achieved.

公开(公告)号：JP2004294383A

公开(公告)日：2004-10-21

申请号：JP2003090356

申请日：2003-03-28

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ONISHI MICHIHIRO ,  MAMINE TAKAYOSHI ,  YUBI HIROSHI ,  SAKAMOTO YASUHIRO

IPC: G01N33/53 ,  C12M1/00 ,  C12N15/09 ,  G01N33/543 ,  G01N37/00

Abstract: PROBLEM TO BE SOLVED: To prevent reaction efficiency from being reduced by steric hindrance during mutual reactive actions among molecules by fixing detecting molecules in moderate density.
SOLUTION: A detection surface 1 is formed on a substrate 2 facing a reaction region R which provides an intermolecular mutual reactive action field between detecting molecules D, having a thiol group (-SH) or a disulfide group (-S-S-) and target molecules T for specifically reacting with the detecting molecules D. Island-like metal thin film 11 of, such as gold, are formed scattered on the detection surface 1 with intervals, and the detection surface 1 of the mutual reactive action between the molecules is provided so as to fix the detecting molecules D to the metal thin film 11 via the mercapto group or the disulfide group.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JPH07147219A

公开(公告)日：1995-06-06

申请号：JP29356593

申请日：1993-11-24

Applicant: SONY CORP

Inventor： YAGI HAJIME ,  SAKAMOTO YASUHIRO

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065

Abstract: PURPOSE:To enable using both of positive type resist and negative type resist, and form a pattern finer than the resolution limit of a pattern. CONSTITUTION:In the method of forming a photoresist pattern by exposing phtoresist on a substrate a plurality of times by using a specified mask pattern, photoresist is exposed by using a plurality of exposure patterns, a photoresist pattern is formed, and then the photoresist pattern is made fine by using plasma ashing.

公开(公告)号：JPS6457771A

公开(公告)日：1989-03-06

申请号：JP21471087

申请日：1987-08-28

Applicant: SONY CORP

Inventor： SAKAMOTO YASUHIRO

IPC: G11B7/125 ,  H01S5/042 ,  H01S5/068

Abstract: PURPOSE:To always grasp an operating state and to obtain information of maintenance whether it is normal deterioration or abnormality by comparing a monitoring output with one of a plurality of comparison reference values, and sequentially comparing it with other comparison reference value to detect the operating state. CONSTITUTION:It is applied to a semiconductor laser device having an APC circuit including a current limiter to detect a deterioration or an abnormality, for example, in two stages. A first comparison reference voltage V2 is set to a value lower than a monitoring voltage at normal time. When a laser diode 1 is deteriorated to reduce a monitoring voltage V0, the output of a comparator 24 is inverted. The deterioration or abnormality of first stage of the diode 1 is notified to an exterior. A second comparison reference voltage V3 is set to a value lower than the first voltage. When the deterioration of the diode 1 is advanced so that the voltage V0 is further reduced, the output of the comparator 30 is inverted. The deterioration or abnormality of second stage is notified.