公开(公告)号：FR2505589A1

公开(公告)日：1982-11-12

申请号：FR8208014

申请日：1982-05-07

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  NOGUCHI TAKASHI ,  OHTSU TAKAJI

IPC: H04N5/14 ,  H03G1/00 ,  H04N5/243 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/372 ,  H04N5/374 ,  H04N5/378 ,  H04N3/15

Abstract: Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element, and scanning circuits for supplying horizontal and vertical scanning pulses. The picture unit elements in turn discharge a signal charge onto vertical and horizontal transmitting lines in response to the vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to provide a strong output video signal with a good S/N ratio, a current mirror circuit, formed of an input transistor and an output transistor with first current-carrying electrodes joined together to a voltage reference point and with control electrodes joined together, amplifies the signal current. A second current-carrying electrode of the input transistor receives a constant current from a current source and also receives the signal current. The output transistor has a second current-carrying electrode connected to an output load. Another current source can be connected to the output transistor so that only AC current will flow to the output load. The output load can be a load capacitor associated with a pre-charging transistor, or can be a serial charge transfer device.

公开(公告)号：CA1125391A

公开(公告)日：1982-06-08

申请号：CA343314

申请日：1980-01-09

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO

IPC: G11C27/04 ,  G11C19/28 ,  G11C27/00 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/772 ,  H03H7/30 ,  H03H15/02 ,  H03H17/00

Abstract: A filter circuit of the type utilizing a chargetransfer device, such as a bucket brigade device, comprises a clocking signal drive circuit for supplying a clocking signal; a clock signal generator at whose output a clocking control signal is provided; a transistor whose base is connected to the output of the clock signal generator; a plurality of successive capacitive storage stages for sequentially holding a charge level representing a time-sampled input signal, each of the capacitive storage stages having a clocking electrode for receiving the clocking signal so that the charge level is transferred from one to another of the capacitive storage stages in succession, and at least one of the capacitive storage stages being formed of first and second parallel-connected capacitive circuit portions, and the first and second capacitive circuit portions having respective clocking electrodes coupled to the clock signal generator and to the emitter of the transistor, respectively; and a current feedback circuit, such as a current mirror circuit, for detecting the current flowing through the collector of the transistor and applying a corresponding current to a capacitive storage stage in advance of that stage which is coupled to the emitter of the transistor.

公开(公告)号：DE3002705A1

公开(公告)日：1980-08-07

申请号：DE3002705

申请日：1980-01-25

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO

IPC: H03H15/02 ,  H03H7/28

Abstract: A non-recursive transversal filter circuit employs a charge transfer device in which certain of the capacitive storage elements are divided into first and second capacitive portions having predetermined capacitance relationships. The charge in the second capacitive storage elements is sensed at predetermined times to produce an output signal. The relative capacitances of the second capacitance portions provide weighting factors to the filter. Embodiments include bucket brigade devices with bipolar and FET transistors as well as charge coupled devices.

公开(公告)号：AU5500180A

公开(公告)日：1980-07-31

申请号：AU5500180

申请日：1980-01-29

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO

IPC: H03H15/02 ,  H03H15/00 ,  H03H11/26

Abstract: A non-recursive transversal filter circuit employs a charge transfer device in which certain of the capacitive storage elements are divided into first and second capacitive portions having predetermined capacitance relationships. The charge in the second capacitive storage elements is sensed at predetermined times to produce an output signal. The relative capacitances of the second capacitance portions provide weighting factors to the filter. Embodiments include bucket brigade devices with bipolar and FET transistors as well as charge coupled devices.

公开(公告)号：ID18396A

公开(公告)日：1998-04-02

申请号：ID963235

申请日：1996-11-08

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  RI AKIRQA

IPC: H02M3/07 ,  H01J29/86

Abstract: An internal power supply circuit, comprising a plurality of charge accumulators (C1 - C3), a first power supply terminal (Vcc), a second power supply terminal (GND), a first switch (NUi, NLi) for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch (PT1 - PT3) for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at the first state and the first state and the second state set repeatedly to raise a voltage between the first power supply terminal and the second power supply terminal.

公开(公告)号：DE3775508D1

公开(公告)日：1992-02-06

申请号：DE3775508

申请日：1987-09-21

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: G11C11/412 ,  G11C11/40 ,  G11C11/401

Abstract: A memory cell circuit has a pair of transistors (M1, M2) in which the gates are connected to the drains, a first and a second access transistor (M3, M4) whose gates are connected to a read line (WL) and which are located between gate-drain connections of said pair of transistors and a pair of bit lines (BL1, BL2). The memory cell circuit also includes a third access transistor (M5) whose gate is connected to the read line (WL) and is located in the circuit between said first access transistor (M3) and the gate of said pair of transistors corresponding to the first access transistor (M3), and a fourth access transistor (M6) whose gate is connected to the read line (WL) and is located in the circuit between said second access transistor (M4) and the gate of said pair of transistors corresponding to the second access transistor.

公开(公告)号：DE3581192D1

公开(公告)日：1991-02-07

申请号：DE3581192

申请日：1985-09-12

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  HAZAMA YOSHIKAZU

IPC: H04N5/66 ,  G02F1/133 ,  G09G3/36

Abstract: PCT No. PCT/JP85/00508 Sec. 371 Date May 12, 1986 Sec. 102(e) Date May 12, 1986 PCT Filed Sep. 12, 1985 PCT Pub. No. WO86/01926 PCT Pub. Date Mar. 27, 1986.According to the present invention, in a liquid crystal display apparatus, there are provided second horizontal switching elements MBl to MBm, which are driven at the advanced phase relative to picture element switching signals phi Hl to phi Hm, at columns Ll to Lm to which a video signal is supplied, a signal, which is derived through said second horizontal switching elements MBl to MBm, is fed back through an inverting circuit (14) and the like to an input terminal (1), and there are provided third switching elements MRl to MRm which are turned on at every predetermined period. According to this apparatus, since a signal derived from a liquid crystal cell C is returned to the same liquid crystal cell C, the displacement of the picture and the like can be avoided, any special scanning and the like are not required and a prior art driving circuit and so on can be used as they are. Further, since the potential of the signal line is reset at every predetermined period, it is possible to prevent the quality of the picture from being deteriorated by a residual charge and the like and the excellent display of a still picture can be carried out over a long time period.

公开(公告)号：GB2190808A

公开(公告)日：1987-11-25

申请号：GB8708490

申请日：1987-04-09

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: G11C11/419 ,  G11C7/06 ,  H03K3/011 ,  H03K3/356 ,  H03K5/02

Abstract: An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of the PMOS and NMOS transistors so that divergence in the threshold voltages can be compensated for.

公开(公告)号：DE3366801D1

公开(公告)日：1986-11-13

申请号：DE3366801

申请日：1983-04-16

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  MAEKAWA TOSHIKAZU ,  OHTSU KOJI

IPC: H01L27/146 ,  H04N5/374 ,  H04N5/30 ,  H01L27/14 ,  H04N3/15

公开(公告)号：AU552787B2

公开(公告)日：1986-06-19

申请号：AU8461782

申请日：1982-06-07

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  OTSU TAKAJI ,  KUTARAGI KEN

IPC: H04N5/30 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G09F9/35 ,  H04N5/66

Abstract: A liquid crystal matrix display device has a plurality of liquid crystal display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to compensate for crosstalk that occurs because of parasitic capacitance between the vertical transmitting lines and the liquid crystal display elements, auxiliary lines are provided for the columns of such display elements, and each has a predetermined compensating capacitance relative to its associated liquid crystal display elements. A compensating signal, which is an inverted version of the video signal, is applied in succession to the auxiliary lines to compensate for any crosstalk.