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    21.
    发明专利
    未知

    公开(公告)号：FR2803100A1

    公开(公告)日：2001-06-29

    申请号：FR9916604

    申请日：1999-12-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： TAILLIET FRANCOIS

    IPC: H01L27/02 ,  H01L23/60 ,  H01L21/8229

    Abstract: The protection device for an interconnection line of an integrated circuit includes a charge flow-off device connected between the interconnection line to be protected and the substrate of the integrated circuit. The protection device also includes a dummy interconnection line ANT to activate the flow-off device. The protection device is active throughout the manufacture of the integrated circuit.

    22.
    发明专利
    未知

    公开(公告)号：DE3856420T2

    公开(公告)日：2000-12-07

    申请号：DE3856420

    申请日：1988-10-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： KOWALSKI JACEK ,  TAILLIET FRANCOIS

    IPC: H01L23/60 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/866 ,  H01L29/72

    Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

    23.
    发明专利
    未知

    公开(公告)号：DE3856420D1

    公开(公告)日：2000-08-24

    申请号：DE3856420

    申请日：1988-10-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： KOWALSKI JACEK ,  TAILLIET FRANCOIS

    IPC: H01L23/60 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/866 ,  H01L29/72

    Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

    Neutralizing device for repetition rate of integrated electronic circuit controlled by timing signal, uses two monostable circuits which produce pulses from timing signal with rising and falling pulse edges
    24.
    发明专利
    Neutralizing device for repetition rate of integrated electronic circuit controlled by timing signal, uses two monostable circuits which produce pulses from timing signal with rising and falling pulse edges 未知

    公开(公告)号：FR2783985A1

    公开(公告)日：2000-03-31

    申请号：FR9812187

    申请日：1998-09-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： TAILLIET FRANCOIS

    IPC: H03K5/1252 ,  H03K5/19 ,  G06F1/04

    Abstract: The device neutralizes a timing signal anomaly for an integrated circuit set by the timing signal (H). This is for anomalies for a timing pulse signal duration of less than a first step value (t1min), or a duration between two timing pulses less than a second step value (t2min). The anomaly sensor (1) activates an inhibiting mechanism when the anomaly is detected in the timing signal. The device includes a first monostable circuit (4) receiving on an input the timing signal (H), and delivering at an output, for each falling edge of the timing signal, of a pulse whose duration is equal to the second value (t2min). There is a second monostable circuit (5) receiving on an input the signal, and delivering at an output, for each rising front of the timing signal (H), of a pulse whose duration is equal to the first value (t1min)'. A logic circuit (6) processes the two pulses and sends a trigger pulse to the inhibit each time the timing signal produces an anomaly.

    Method, integrated circuit and test system for adjusting internal timing or associated reference quantity in integrated circuits, for use in particular in read-only memory circuits
    27.
    发明专利
    Method, integrated circuit and test system for adjusting internal timing or associated reference quantity in integrated circuits, for use in particular in read-only memory circuits 未知

    公开(公告)号：FR2818424A1

    公开(公告)日：2002-06-21

    申请号：FR0016703

    申请日：2000-12-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： TAILLIET FRANCOIS

    IPC: G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G01R31/00 ,  G01R31/303

    Abstract: The method for adjusting the duration of internal timing to a value close to the typical value (T0) of that duration includes the inducement of internal timing (TEMP) in an integrated circuit, and the sending of calibration values (K1,K2,...K40) in sequence from a tester to the input of the integrated circuit. The expiration of internal timing determines the calibration datum (K) as the last received calibration value or that in the train of received values, which is applied to an adjustment device (AJUST) for adjusting the duration of internal timing in the integrated circuit (CI). The integrated circuit comprises an internal timing generator circuit (GEN-TEMP) operated on the basis of a reference quantity such as current or capacitance (IREF, CREF), a register (REG) for temporary storage of calibration values input as data from the tester, a control circuit (CL) receiving the test instructions, and a memory element M(KE) for storing the calibration datum. Each calibration value corresponds to a ratio of the typical value (T0) to the total time lapsed from the start of internal timing to the instant when the value is sent. The device for adjustment is initialized to a calibration value, and each calibration value sent is affected by the initialization value. The first calibration value is sent after a lapse of a minimum duration of internal timing. The adjusted reference circuit is a current source, a network of capacitors, or a network of resistors. The method is applied to a read-only memory integrated circuit for adjusting the duration of programming signal. The method includes the launch of programming of any data at an address in the integrated circuit, and sending of calibration values as data to the input of integrated circuit. The method includes the programming of the calibration datum after sending all calibration values defined for the internal timing a function of specifications of the integrated circuit. The system for testing in parallel of integrated circuits of the same technology comprises a table (TAB) of calibration values for adjusting the internal timing.

    Device for memory programming comprises means for application of erasing and writing voltages to floating-gate transistors in memory cells
    29.
    发明专利
    Device for memory programming comprises means for application of erasing and writing voltages to floating-gate transistors in memory cells 未知

    公开(公告)号：FR2792761A1

    公开(公告)日：2000-10-27

    申请号：FR9905051

    申请日：1999-04-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： TAILLIET FRANCOIS

    IPC: G11C16/30 ,  G11C16/06 ,  H02M3/07

    Abstract: The device for programming an electrically programmable memory comprises means for the application of two voltages (Vppc, Vppw) to the memory cells each containing a floating-gate transistor, for the operation of erasing and writing, wherein the two voltages are determined so that the electric fields are of the same absolute value in the erasing and writing operations. The device comprises a programming unit (1) for the generation of two voltages, and a selection circuit (2) connected to one or more cells of the memory unit (3). The programming unit (1) comprises a charging circuit (10) generating a high voltage (VHI), a sawtooth voltage generator (20) delivering programming voltage (Vpp), and a control circuit (30) for the control of programming voltage with respect to reference voltages (V1,V2) corresponding to the erasing and writing voltages (Vppe, Vppw). The programming voltage (Vpp) is applied to the input (E) of the control circuit (30) which contains a simulation (31) of the selection circuit (2), so that the voltage (Vpps) is normally equal to the voltage (Vpp'), and means for comparing the input voltage to the reference voltages (V1,V2). In the second embodiment, the programming unit also comprises means for the control of the high voltage (VHI) with respect to a third reference voltage, which is higher than the two reference voltages (V1,V2). The control circuit (30) contains a set of diodes, e.g. 3 Zener diodes and one MOS transistor connected as diode, connected in series and reverse, a switching circuit, and a comparator circuit delivering the control signal (Run) applied to the charging circuit (10). In the second embodiment, the control circuit contains a second set of diodes, e.g. 3 Zener diodes and 2 MOS transistors connected as diodes, in series and reverse, for the definition of the third reference voltage.

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