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公开(公告)号：DE69800785T2
公开(公告)日：2002-03-07
申请号：DE69800785
申请日：1998-07-03
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: A detection circuit for access anomalies in microcontroller cell access consists of a central information processor (14), at least one RAM (18) of which part (26) is reserved for the cell, an input/output circuit (20) and a communication bus (22). The circuit incorporates a first detector 28) for all access to the cell (26), a second detector (32, 34) for any instruction giving access to the cell and an alarm signal generator (46) for when any access to the cell is detected outside an instruction containing such access. It also has a means (20) of interrupting the function of the micro-controller when an alarm signal is given.
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公开(公告)号：DE69426477T2
公开(公告)日：2001-04-19
申请号：DE69426477
申请日：1994-08-01
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , DO TIEN-DUNG
IPC: H03K5/19 , H03K5/1252 , H03K5/13 , H03K5/01
Abstract: A circuit for filtering a pulse signal comprises means for generating an output pulse CLKOUT upon detection of an input pulse CLKIN, the shape of this output pulse being based on elementary delays obtained by charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.
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公开(公告)号：DE60128646D1
公开(公告)日：2007-07-12
申请号：DE60128646
申请日：2001-11-03
Applicant: ST MICROELECTRONICS SA
Inventor： MARINET FABRICE , WUIDART SYLVIE
Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.
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公开(公告)号：DE602004000226T2
公开(公告)日：2006-07-06
申请号：DE602004000226
申请日：2004-01-27
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , ZAHRA CLAUDE
IPC: G01R31/28 , G01R31/3193 , G01R31/3185
Abstract: A number of integrated circuit chips are connected in parallel with a testing equipment which issues a first test command CTRL1 (20). The tests are then made asynchronously PROCESS1 (21) and the integrated circuits wait WAIT CONTROL2 (22). After a time interval the testing equipment asks for a reply SEND CTRL2 (23) and there is a synchronous reply SEND ANSW (24). An independent claim is also included for: A system which has pairs of contacts to connect integrated circuits in parallel with a testing equipment and integrated circuits able to respond to a synchronous operation command.
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公开(公告)号：DE602004000226D1
公开(公告)日：2006-01-19
申请号：DE602004000226
申请日：2004-01-27
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , ZAHRA CLAUDE
IPC: G01R31/28 , G01R31/3185 , G01R31/3193
Abstract: A number of integrated circuit chips are connected in parallel with a testing equipment which issues a first test command CTRL1 (20). The tests are then made asynchronously PROCESS1 (21) and the integrated circuits wait WAIT CONTROL2 (22). After a time interval the testing equipment asks for a reply SEND CTRL2 (23) and there is a synchronous reply SEND ANSW (24). An independent claim is also included for: A system which has pairs of contacts to connect integrated circuits in parallel with a testing equipment and integrated circuits able to respond to a synchronous operation command.
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Patent Agency Ranking
公开(公告)号：DE60113721D1
公开(公告)日：2005-11-03
申请号：DE60113721
申请日：2001-12-19
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.
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公开(公告)号：DE60103397T2
公开(公告)日：2005-06-02
申请号：DE60103397
申请日：2001-05-28
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
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公开(公告)号：FR2819070B1
公开(公告)日：2003-03-21
申请号：FR0017261
申请日：2000-12-28
Applicant: ST MICROELECTRONICS SA
Inventor： MARINET FABRICE , WUIDART SYLVIE
IPC: G06F21/55 , G06F12/14 , G06K19/073
Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.
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公开(公告)号：FR2818845B1
公开(公告)日：2003-03-21
申请号：FR0016747
申请日：2000-12-21
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
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公开(公告)号：DE69526753D1
公开(公告)日：2002-06-27
申请号：DE69526753
申请日：1995-07-27
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , SOURGEN LAURENT
IPC: G06F21/22 , G06F1/00 , G06F7/76 , G06F21/00 , G09C1/00 , H01L27/10 , G06F12/14 , G06F7/00 , H01L23/535
Abstract: The method involves using an executable code generator for discriminating between program instructions and program data, and for bit-scrambling the instructions. The resulting code is loaded into a programmable memory connected by the data bus to a controller. Program code is sent in scrambled form over the data bus, and is de-scrambled by a controller (DBR1,RI) for delivery to a processor (UP). A re-writable memory clears data, which is carried on the data bus and scrambles (DBR2,DBR3) data for storage. The data is unscrambled when read from storage. The scrambling algorithms for program code and for data are different.
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