公开(公告)号：DE69833247D1

公开(公告)日：2006-04-06

申请号：DE69833247

申请日：1998-10-02

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, which method comprises at least the following steps: on a semiconductor substrate, defining respective active areas for transistors of ROM cells (1), electrically erasable non-volatile memory cells, and low- and high-voltage transistors; depositing a layer of gate oxide over said active areas; depositing a polysilicon layer over the gate oxide layer; masking, and then etching, the polysilicon layer to define, by successive steps, respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors; characterized in that it further comprises the following steps: masking the polysilicon layer (4) of some of the transistors of the ROM cells (1), and implanting a first dopant species (N) in the active areas (2) of the exposed transistors; removing the mask from the polysilicon layer (4), and implanting a second dopant species (P) in said previously covered layer; masking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors.

公开(公告)号：ITVA20030052A1

公开(公告)日：2005-06-24

申请号：ITVA20030052

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： BASSI MASSIMO ,  PATELMO MATTEO ,  PORTOGHESE ROSARIO ,  SCURATTI STEFANO

IPC: G11C5/00 ,  G11C29/00 ,  G11C29/50

公开(公告)号：IT1313198B1

公开(公告)日：2002-06-17

申请号：ITMI991617

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLA LIBERA GIOVANNA ,  PATELMO MATTEO

IPC: H01L27/115

Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

公开(公告)号：IT1311325B1

公开(公告)日：2002-03-12

申请号：ITTO991112

申请日：1999-12-17

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

IPC: H01L29/78

Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region. Therefore, the transistor has a channel region which is delimited between the source region and drain region and one half of which has a first doping level and the other half a second doping level greater than the first doping level; consequently, the transistor has a high threshold voltage.

公开(公告)号：ITTO991112A1

公开(公告)日：2001-06-18

申请号：ITTO991112

申请日：1999-12-17

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

IPC: H01L29/78

Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region. Therefore, the transistor has a channel region which is delimited between the source region and drain region and one half of which has a first doping level and the other half a second doping level greater than the first doping level; consequently, the transistor has a high threshold voltage.