公开(公告)号：JP2000133729A

公开(公告)日：2000-05-12

申请号：JP30259599

申请日：1999-10-25

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable integration of all together a nonvolatile memory cell and a high- speed transistor subjected to salicide processing, by forming firstly the region to form a high-voltage transistor, and by forming thereafter the region to form a low-voltage transistor. SOLUTION: Into a sacrificial oxide layer 10 present on a substrate 2, N-type ionized dopants are injected using a mask for forming an H-HV region of a high-voltage(HV) PMOS transistor. Then, after masking the entire surface of a wafer 1 while leaving an HV active region and an array active region, P-type ionized dopants are injected thereinto to form a P-HV region 13 of an HV transistor and form a P-matrix region 14 of a memory cell. Subsequently, N-type ionized dopants are injected into the layer 10, using a mask to form an N-LV region of a low-voltage(LV) PMOS transistor. Continuously, after masking the entire surface of the wafer 1, leaving an LV active region, P-type ionized dopants 18 are injected thereinto to form P-LV region 19 of an L V-NMOS transistor.

公开(公告)号：JP2000058800A

公开(公告)日：2000-02-25

申请号：JP20822399

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a manufacture of a simple inexpensive non-volatile cell and s high speed transistor. SOLUTION: This manufacture includes the steps of depositing the upper layer of a polycrystalline silicon; defining the upper layer to form a part not defined and the low voltage(LV) gate region 43a of a low voltage transistor; forming LV source and drain regions 55 in the side of the LV gate region 43a; forming silicide layers 57a1, 57a2, 57 over the LV source and drain regions 55, the LV gate region 43a, and the part not defined; defining the laminated gate regions 43b, 43c of a high voltage(HV) transistor and a HV gate region 43d; and forming HV source and drain regions and a cell region.

公开(公告)号：JP2000114398A

公开(公告)日：2000-04-21

申请号：JP28181799

申请日：1999-10-01

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To obtain a method for manufacturing a ROM memory cell, which can store at least three different logical levels by doping two different points of a polycrystalline silicon layer forming the gate region of a transistor. SOLUTION: This method includes steps in which several polycrystalline silicone layers of transistors of a ROM cell 1 are masked, a step of implanting impurities of first type N into an exposed active region 2 of the transistors, a step of removing the mask from the polycrystalline silicon layers and implanting impurities of second type P into a layer covered previously and a step of masking the polycrystalline silicon layer, then performing etching for determining the gate region of the transistors of the ROM cell.

公开(公告)号：DE69841670D1

公开(公告)日：2010-07-01

申请号：DE69841670

申请日：1998-10-23

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

公开(公告)号：DE69821939D1

公开(公告)日：2004-04-01

申请号：DE69821939

申请日：1998-10-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor; growth of tunnel oxide; Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

公开(公告)号：DE69833247D1

公开(公告)日：2006-04-06

申请号：DE69833247

申请日：1998-10-02

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, which method comprises at least the following steps: on a semiconductor substrate, defining respective active areas for transistors of ROM cells (1), electrically erasable non-volatile memory cells, and low- and high-voltage transistors; depositing a layer of gate oxide over said active areas; depositing a polysilicon layer over the gate oxide layer; masking, and then etching, the polysilicon layer to define, by successive steps, respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors; characterized in that it further comprises the following steps: masking the polysilicon layer (4) of some of the transistors of the ROM cells (1), and implanting a first dopant species (N) in the active areas (2) of the exposed transistors; removing the mask from the polysilicon layer (4), and implanting a second dopant species (P) in said previously covered layer; masking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors.

公开(公告)号：DE69841040D1

公开(公告)日：2009-09-17

申请号：DE69841040

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  VAJANA BRUNO ,  DALLA LIBERA GIOVANNA ,  CREMONESI CARLO ,  GALBIATI NADIA

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105

Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

公开(公告)号：DE69840541D1

公开(公告)日：2009-03-26

申请号：DE69840541

申请日：1998-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  GALBIATI NADIA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

IPC: H01L21/8234 ,  H01L21/8239 ,  H01L27/105

公开(公告)号：DE69832162D1

公开(公告)日：2005-12-08

申请号：DE69832162

申请日：1998-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  GALBIATI NADIA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

IPC: H01L27/06 ,  H01L21/8234

Abstract: The manufacture process comprises the following steps in succession: depositing a gate oxide layer on a silicon substrate (2) defining a transistor area (5) and a resistor area (6); depositing a multicrystal silicon layer (11) on the gate oxide layer (10); removing selective portions of the multicrystal silicon layer (11) to form a gate region (11a) over the transistor area (5) and a protective region (11b) completely covering the resistor area (6); forming source and drain regions (22) in the transistor area (5), laterally to the gate region (11a); forming silicide regions (25, 26 and 27) on and in direct contact with the source and drain regions (22), the gate region (11a) and the protective region (11b); removing selective portions of the protective region (11b) to form a delimitation ring (34); and implanting ionic dopants in the resistor area (6), inside the area defined by the protective ring (34), to form a lightly doped resistor (38) which has no silicide regions directly on it.

公开(公告)号：IT1302589B1

公开(公告)日：2000-09-29

申请号：ITMI982124

申请日：1998-10-02

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8238

Abstract: In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for low-voltage and high-voltage transistors. A gate oxide layer and a layer of polysilicon is deposited over the substrate, which is masked and etched to produce gates for the transistors. A dielectric layer is deposited to produce spacers to the sides of the transistor gate regions, then a mask partially shields the dielectric layer over the junctions of the high-voltage transistors while the spacers are being formed. Finally, the substrate is doped in the gate and active areas of the high-voltage transistor, and in the gate and active areas of the low-voltage transistor, except those areas that are blocked by the spacers.