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    MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE
    2.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE 失效

    公开(公告)号：JPH1174490A

    公开(公告)日：1999-03-16

    申请号：JP17749698

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  PIO FEDERICO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a simple manufacturing method of a semiconductor memory device having storage memory cells and shielded memory cells shielded so as to prevent their stored informations from being read out by external systems. SOLUTION: In the same chip made of semiconductor materials, there are formed at least one first memory cells each of which has a MOS transistor with overlapping first and second gates with each other formed respectively in first and second conductive material layers 12, 17 and at least one second memory cells each of which is so shielded by a shield material layer 32 that no external system can access to its storing information. This second memory cell comprises a MOS transistor having a floating gate formed of the first conductive material layer 12 simultaneously with the foregoing first gate electrode of the foregoing first memory cell, and the shield material layer 32 is formed of the second conductive material layer 17.

    ELECTRONIC DEVICE CONSISTING OF NONVOLATILE MEMORY CELLS WITH DIMENSIONAL CONTROL OF FLOATING GATE REGION AND MANUFACTURE THEREOF
    4.
    发明专利
    ELECTRONIC DEVICE CONSISTING OF NONVOLATILE MEMORY CELLS WITH DIMENSIONAL CONTROL OF FLOATING GATE REGION AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2001044303A

    公开(公告)日：2001-02-16

    申请号：JP2000218914

    申请日：2000-07-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VAJANA BRUNO ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To eliminate the critical and complicated step of removing a residual material produced during demarcating a second polycrystalline layer, by simultaneously forming floating gate regions of a memory transistor and a lower gate portion which is arranged at a location adjacent to but distant from the floating gate regions, on top of first dielectric material layers. SOLUTION: Floating gate regions 35" of a memory transistor 80 and a lower gate portion 35' are formed simultaneously on top of first dielectric material layers 24 and 26 provided with a tunnel region 24. The region 35' is arranged at a location adjacent to but is located further distant from the region 35". Insulating structural bodies 40a and 41 for enclosing the regions 35" are formed. Then, a control gate region 50a and an upper gate region 50b are formed simultaneously on top of the bodies 40a and 41 and on top of the region 35', respectively. The regions 35" are provided with a hole covered with a dielectric material, and a selective transistor 81 is provided with the region 35' and the region 50b.

    7.
    发明专利
    未知

    公开(公告)号：DE69821939D1

    公开(公告)日：2004-04-01

    申请号：DE69821939

    申请日：1998-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

    Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor; growth of tunnel oxide; Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

    10.
    发明专利
    未知

    公开(公告)号：ITTO991112D0

    公开(公告)日：1999-12-17

    申请号：ITTO991112

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

    IPC: H01L29/78

    Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region. Therefore, the transistor has a channel region which is delimited between the source region and drain region and one half of which has a first doping level and the other half a second doping level greater than the first doping level; consequently, the transistor has a high threshold voltage.

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