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29 records (took 0.023 seconds)

    21.
    发明专利
    未知

    公开(公告)号：ITMI990331A1

    公开(公告)日：2000-08-18

    申请号：ITMI990331

    申请日：1999-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE

    IPC: H01L27/07 ,  H01L29/73

    Abstract: The device is constituted by an N+ substrate, by an N- layer on the substrate, by a metal contact for a collector, by a buried P- base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

    25.
    发明专利
    未知

    公开(公告)号：IT1316871B1

    公开(公告)日：2003-05-12

    申请号：ITMI20000688

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE

    IPC: H01L27/07

    Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

    26.
    发明专利
    未知

    公开(公告)号：IT1311280B1

    公开(公告)日：2002-03-12

    申请号：ITTO991151

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SANFILIPPO DELFO ,  PATTI DAVIDE

    IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

    Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

    27.
    发明专利
    未知

    公开(公告)号：ITTO991151A1

    公开(公告)日：2001-06-25

    申请号：ITTO991151

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  SANFILIPPO DELFO

    IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

    Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

    29.
    发明专利
    未知

    公开(公告)号：ITTO991151D0

    公开(公告)日：1999-12-24

    申请号：ITTO991151

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  SANFILIPPO DELFO

    IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

    Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

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