公开(公告)号：ITMI982146A1

公开(公告)日：2000-04-07

申请号：ITMI982146

申请日：1998-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： LEONARDI SALVATORE ,  PATTI DAVIDE ,  SANFILIPPO DELFO

IPC: H01L20060101

公开(公告)号：ITTO990454A1

公开(公告)日：2000-11-28

申请号：ITTO990454

申请日：1999-05-28

Applicant: ST MICROELECTRONICS SRL

Inventor： SANFILIPPO DELFO ,  LEONARDI SALVATORE

IPC: H01L21/762

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

公开(公告)号：IT1311280B1

公开(公告)日：2002-03-12

申请号：ITTO991151

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： SANFILIPPO DELFO ,  PATTI DAVIDE

IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

公开(公告)号：IT1308063B1

公开(公告)日：2001-11-29

申请号：ITTO990454

申请日：1999-05-28

Applicant: ST MICROELECTRONICS SRL

Inventor： SANFILIPPO DELFO ,  LEONARDI SALVATORE

IPC: H01L21/762

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

公开(公告)号：ITTO991151A1

公开(公告)日：2001-06-25

申请号：ITTO991151

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE ,  SANFILIPPO DELFO

IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

公开(公告)号：IT1302610B1

公开(公告)日：2000-09-29

申请号：ITMI982146

申请日：1998-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： LEONARDI SALVATORE ,  PATTI DAVIDE ,  SANFILIPPO DELFO

IPC: H01L20060101

公开(公告)号：ITTO991151D0

公开(公告)日：1999-12-24

申请号：ITTO991151

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE ,  SANFILIPPO DELFO

IPC: H01C7/10 ,  H01C17/075 ,  H01L21/02 ,  H01L27/08

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.