公开(公告)号：EP0942374B1

公开(公告)日：2003-03-05

申请号：EP99301876.1

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3664 ,  G06F11/261 ,  G06F11/3648

公开(公告)号：EP0953915A1

公开(公告)日：1999-11-03

申请号：EP99303254.9

申请日：1999-04-27

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  May, Michael David

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A chip (11) with an address and data path (15) interconnecting at least one CPU (12) with another module (14) and an external communication port (30), the CPU generating event packets and memory access packets and the module (14) generating event packets, the packets being distributed in parallel format on the path 15 and the external communication port (30) including circuitry to reduce the parallel format of each packet to a more serial format for off-chip communication.

Abstract translation: 具有将至少一个CPU（12）与另一模块（14）和外部通信端口（30）互连的地址和数据路径（15）的芯片（11），所述CPU生成事件分组和存储器访问分组以及所述模块 14）生成事件分组，分组以并行格式分布在路径15上，外部通信端口（30）包括电路，以将每个分组的并行格式减小到更多的串行格式用于片外通信。